Antonio Rubio
Orcid: 0000-0003-1625-1472Affiliations:
- Polytechnic University of Catalonia (UPC), Department of Electronic Engineering, Barcelona, Spain
According to our database1,
Antonio Rubio
authored at least 140 papers
between 1991 and 2024.
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Bibliography
2024
CBRAM-Based Bio-Inspired Circuit for the Emulation and Treatment of the Parkinson's Disease.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
2023
J. Syst. Archit., 2023
MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization.
IEEE Access, 2023
IEEE Access, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Hardware Design of Memristor-based Oscillators for Emulation of Neurological Diseases.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
On the Development of Prognostics and System Health Management (PHM) Techniques for ReRAM Applications.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact.
IEEE Access, 2022
A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Exploring Different Circuit-level Approaches to the Forming of Resistive Random Access Memories.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Two examples of approximate arithmetic to reduce hardware complexity and power consumption.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
Power-Efficient Noise-Induced Reduction of ReRAM Cell's Temporal Variability Effects.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Access, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Shortest Path Computing in Directed Graphs with Weighted Edges Mapped on Random Networks of Memristors.
Parallel Process. Lett., 2020
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells.
IEEE Access, 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
IEEE Trans. Emerg. Top. Comput., 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
Experimental Study of Artificial Neural Networks Using a Digital Memristor Simulator.
IEEE Trans. Neural Networks Learn. Syst., 2018
IEEE Trans. Emerg. Top. Comput., 2018
Optimization of FinFET-Based Gain Cells for Low Power Sub-<i>V</i> <sub>T</sub> Embedded DRAMs.
J. Low Power Electron., 2018
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
J. Low Power Electron., 2017
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells.
Proceedings of the 14th International Conference on Synthesis, 2017
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Reliability issues in RRAM ternary memories affected by variability and aging mechanisms.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017
Proceedings of the 2017 IEEE International Conference on Computer Vision Workshops, 2017
Proceedings of the Sixth Workshop on Vision and Language, 2017
2016
Experience on material implication computing with an electromechanical memristor emulator.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 23rd International Conference on Pattern Recognition, 2016
2015
Adaptive Proactive Reconfiguration: A Technique for Process-Variability- and Aging-Aware SRAM Cache Design.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Variability and reliability analysis of CNFET technology: Impact of manufacturing imperfections.
Microelectron. Reliab., 2015
J. Low Power Electron., 2015
Analysis and design of an adaptive proactive reconfiguration approach for memristive crossbar memories.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the IEEE International Conference on Robotics and Automation, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
2014
A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Microelectron. J., 2014
Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Systematic and random variability analysis of two different 6T-SRAM layout topologies.
Microelectron. J., 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy.
Microprocess. Microsystems, 2012
Integr., 2012
Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2011
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011
Microelectron. J., 2011
Design of complex circuits using the Via-Configurable transistor array regular layout fabric.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the CONIELECOMP 2011, 21st International Conference on Electrical, Communications, and Computers, 28 February, 2011
Proceedings of the ARCS 2011, 2011
2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs.
Microelectron. J., 2009
2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 13th European Test Symposium, 2008
2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits.
Microelectron. J., 2005
J. Low Power Electron., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Microelectron. Reliab., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
2003
2002
IEEE Des. Test Comput., 2002
2001
IEEE J. Solid State Circuits, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
1999
IEEE J. Solid State Circuits, 1999
J. Electron. Test., 1999
1998
Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic.
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997
IEEE J. Solid State Circuits, 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
J. Electron. Test., 1996
Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design.
Proceedings of the 1996 European Design and Test Conference, 1996
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Improving Board and System Test: A Proposal to Integrate Boundary Scan and I<sub>DDQ</sub>.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Electrical model of the floating gate defect in CMOS ICs: implications on I<sub>DDQ</sub> testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
An Approach to the Development of a IDDQ Testable Cell Library.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
Analysis of the Floating Gate Defect in CMOS.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992
1991
Proceedings of the conference on European design automation, 1991