Marc Jaikissoon

According to our database, Marc Jaikissoon authored at least 4 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Ultrathin Gate Dielectric Enabled by Nanofog Aluminum Oxide on Monolayer MoS2.

Jung-Soo Ko, Zichen Zhang, Sol Lee, Marc Jaikissoon, Robert K. A. Bennett, Kwanpyo Kim, Andrew C. Kummel, Prabhakar Bandaru, Eric Pop, Krishna C. Saraswat

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

Local Back-Gate Monolayer MoS2 Transistors with Channel Lengths Down to 50 nm and EOT ∼ 1 nm Showing Improved $I_{\text{on}}$ using Post-Metal Anneal.

Marc Jaikissoon, Jung-Soo Ko, Eric Pop, Krishna C. Saraswat

Proceedings of the Device Research Conference, 2023

2022

Mobility Enhancement of Monolayer MoS2 Transistors using Tensile-Stressed Silicon Nitride Capping Layers.

Marc Jaikissoon, Jerry A. Yang, Kathryn M. Neilson, Eric Pop, Krishna C. Saraswat

Proceedings of the Device Research Conference, 2022

2019

3D-stacked Strained SiGe/Ge Gate-All-Around (GAA) Structure Fabricated by 3D Ge Condensation.

Junkyo Suh, Andrew C. Meng, Marc Jaikissoon, Michael Braun, Taeho R. Kim, Ann F. Marshall, Anahita Pakzad, Paul C. McIntyre, Krishna C. Saraswat

Proceedings of the Device Research Conference, 2019