Krishna Saraswat
Affiliations:- Stanford University, USA
According to our database1,
Krishna Saraswat
authored at least 24 papers
between 1995 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1989, "For contributions to metallization and interconnects for VLSI.".
Timeline
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Online presence:
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on id.loc.gov
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Bibliography
2023
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
Local Back-Gate Monolayer MoS2 Transistors with Channel Lengths Down to 50 nm and EOT ∼ 1 nm Showing Improved $I_{\text{on}}$ using Post-Metal Anneal.
Proceedings of the Device Research Conference, 2023
2022
First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (~3 MA/cm<sup>2</sup>) and Low Resistance Drift (~0.002 at 105°C).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the Device Research Conference, 2022
Mobility Enhancement of Monolayer MoS2 Transistors using Tensile-Stressed Silicon Nitride Capping Layers.
Proceedings of the Device Research Conference, 2022
Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties.
Proceedings of the Device Research Conference, 2022
2020
Proceedings of the 2020 Device Research Conference, 2020
2019
3D-stacked Strained SiGe/Ge Gate-All-Around (GAA) Structure Fabricated by 3D Ge Condensation.
Proceedings of the Device Research Conference, 2019
2018
Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2015
50GHz Ge waveguide electro-absorption modulator integrated in a 220nm SOI photonics platform.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
2010
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs.
Proceedings of the NOCS 2010, 2010
2009
Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
2004
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004
Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
2002
Power estimation in global interconnects and its reduction using a novel repeater optimization methodology.
Proceedings of the 39th Design Automation Conference, 2002
2001
Proc. IEEE, 2001
3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration.
Proc. IEEE, 2001
Reliability Studies on Multilevel Interconnection with Intermetal Dielectric Air Gaps.
Microelectron. Reliab., 2001
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
2000
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Proceedings of the 37th Conference on Design Automation, 2000
1995
Flexible Relation: An Approach for Integrating Data from Multiple, Possibly Inconsistent Databases.
Proceedings of the Eleventh International Conference on Data Engineering, 1995