Eric Pop

Orcid: 0000-0003-0436-8534

According to our database1, Eric Pop authored at least 39 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Achieving 1-nm-Scale Equivalent Oxide Thickness Top Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors with CMOS-Friendly Approaches.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Quantifying Defect-Mediated Electron Capture and Emission in Flexible Monolayer WS2 Field-Effect Transistors.
Proceedings of the Device Research Conference, 2024

Optimizing TiTe2/Ge4Sb6Te7 Superlattices Towards Low-Power, Fast-Speed, and High-Stability Phase Change Memory.
Proceedings of the Device Research Conference, 2024

Oxygen Engineering for Positive Bias Stress Stability of Top-Gated Indium Tin Oxide (ITO) Transistors.
Proceedings of the Device Research Conference, 2024

Nanoscale MoS2 Transistors on Polyimide for Radio-Frequency Operation.
Proceedings of the Device Research Conference, 2024

Energy-Efficient Spiking Neural Network Based on Ge4Sb6Te7 Phase-Change Memory Synapses.
Proceedings of the Device Research Conference, 2024

Improved Mobility Extraction for Transistors with Gated Contacts.
Proceedings of the Device Research Conference, 2024

2023
Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Ultrathin Gate Dielectric Enabled by Nanofog Aluminum Oxide on Monolayer MoS2.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

Up to 100-fold Improvement of Threshold Voltage Stability in ITO Transistors.
Proceedings of the Device Research Conference, 2023

Local Back-Gate Monolayer MoS2 Transistors with Channel Lengths Down to 50 nm and EOT ∼ 1 nm Showing Improved $I_{\text{on}}$ using Post-Metal Anneal.
Proceedings of the Device Research Conference, 2023

2022
Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi2Te3 Thermoelectric Interfacial Layer.
Dataset, May, 2022

Stateful Logic using Phase Change Memory.
CoRR, 2022

First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (~3 MA/cm<sup>2</sup>) and Low Resistance Drift (~0.002 at 105°C).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation.
Proceedings of the Device Research Conference, 2022

Mobility Enhancement of Monolayer MoS2 Transistors using Tensile-Stressed Silicon Nitride Capping Layers.
Proceedings of the Device Research Conference, 2022

Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties.
Proceedings of the Device Research Conference, 2022

2020
Flexible Low-Power Superlattice-Like Phase Change Memory.
Proceedings of the 2020 Device Research Conference, 2020

2019
Process-Induced Anomalous Current Transport in Graphene/InA1N/GaN Heterostructured Diodes.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Vertical Sidewall MoS2 Growth and Transistors.
Proceedings of the Device Research Conference, 2019

Large Temperature Coefficient of Resistance in Atomically Thin 2D Devices.
Proceedings of the Device Research Conference, 2019

Flexible Top-Gated Monolayer MoS2 Transistors with High Mobility.
Proceedings of the Device Research Conference, 2019

A Novel ESD Clamp Based on the VO2 Insulator-Metal Transition.
Proceedings of the Device Research Conference, 2019

2018
Investigation of monolayer MX2 as sub-nanometer copper diffusion barriers.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses.
Proceedings of the 76th Device Research Conference, 2018

Sub-Thermionic Steep Switching in Hole-Doped WSe2 Transistors.
Proceedings of the 76th Device Research Conference, 2018

Annealing and Encapsulation of CVD-MoS2 FETs with 10<sup>10</sup>On/Off Current Ratio.
Proceedings of the 76th Device Research Conference, 2018

Probing Self-Heating in RRAM Devices by Sub-100 nm Spatially Resolved Thermometry.
Proceedings of the 76th Device Research Conference, 2018

Localized Heating in Mo'I'ei-Based Resistive Memory Devices.
Proceedings of the 76th Device Research Conference, 2018

Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters.
Proceedings of the 76th Device Research Conference, 2018

2017
Electrons, phonons, and unconventional applications of 2D materials.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2015
Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.
Computer, 2015

2014
Energy efficiency and conversion in 1D and 2D electronics.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2012
Nanoscale power and heat management in electronics.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
A Web Service and Interface for Remote Electronic Device Characterization.
IEEE Trans. Educ., 2011

2006
Heat Generation and Transport in Nanometer-Scale Transistors.
Proc. IEEE, 2006

2005
Thermal simulation techniques for nanoscale transistors.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005


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