Marco A. Peña

Orcid: 0000-0003-0303-8082

According to our database1, Marco A. Peña authored at least 12 papers between 1996 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2021
Urban Growth, Real Estate Development and Indigenous Property: Simulating the Expansion Process in the City of Temuco, Chile.
ISPRS Int. J. Geo Inf., 2021

2005
TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems.
Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2003
Relative timing based verification of concurrent systems.
PhD thesis, 2003

Combining Simulation and Guided Traversal for the Verification of Concurrent Systems.
Proceedings of the 2003 Design, 2003

Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems.
Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002
A Case Study for the Verification of Complex Timed Circuits: IPCMOS.
Proceedings of the 2002 Design, 2002

2000
Formal Verification of Safety Properties in Timed Circuits.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
Structural Methods to Improve the Symbolic Analysis of Petri Nets.
Proceedings of the Application and Theory of Petri Nets 1999, 1999

1997
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment.
Proceedings of the 34st Conference on Design Automation, 1997

Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits.
Proceedings of the 34st Conference on Design Automation, 1997

Partial order based approach to synthesis of speed-independent circuits.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996


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