Alex Kondratyev

According to our database1, Alex Kondratyev
  • authored at least 76 papers between 1988 and 2013.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2013
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Exploiting area/delay tradeoffs in high-level synthesis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Realistic performance-constrained pipelining in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques.
ACM Trans. Design Autom. Electr. Syst., 2010

Incremental high-level synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008
Schedulability Analysis of Petri Nets Based on Structural Properties.
Fundam. Inform., 2008

A Symbolic Algorithm for the Synthesis of Bounded Petri Nets.
Proceedings of the Applications and Theory of Petri Nets, 29th International Conference, 2008

2007
Design Automation of Real-Life Asynchronous Devices and Systems.
Foundations and Trends in Electronic Design Automation, 2007

2006
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Merged processes: a new condensed representation of Petri net behaviour.
Acta Inf., 2006

Schedulability Analysis of Petri Nets Based on Structural Properties.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005
Quasi-Static Scheduling of Concurrent Specifications.
Proceedings of the Embedded Systems Handbook., 2005

Eliminating false positives in crosstalk noise analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Quasi-static scheduling of independent tasks for reactive systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A BMC-based formulation for the scheduling problem of hardware systems.
STTT, 2005

Synthesis methodology for built-in at-speed testing.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A structural approach to quasi-static schedulability analysis of communicating concurrent programs.
Proceedings of the EMSOFT 2005, 2005

Merged Processes - A New Condensed Representation of Petri Net Behaviour.
Proceedings of the CONCUR 2005 - Concurrency Theory, 16th International Conference, 2005

Gaining Predictability and Noise Immunity in Global Interconnects.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
Quasi-static Scheduling for Concurrent Architectures.
Fundam. Inform., 2004

Bridging the Gap between Asynchronous Design and Designers.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Coping with The Variability of Combinational Logic Delays.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Eliminating False Positives in Crosstalk Noise Analysis.
Proceedings of the 2004 Design, 2004

From Synchronous to Asynchronous: An Automatic Approach.
Proceedings of the 2004 Design, 2004

The best of both worlds: the efficient asynchronous implementation of synchronous specifications.
Proceedings of the 41th Design Automation Conference, 2004

Handshake Protocols for De-Synchronization.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
A BMC-formulation for the scheduling problem in highly constrained hardware Systems.
Electr. Notes Theor. Comput. Sci., 2003

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling.
Proceedings of the 2003 Design, 2003

Gain-based technology mapping for discrete-size cell libraries.
Proceedings of the 40th Design Automation Conference, 2003

Temporofunctional crosstalk noise analysis.
Proceedings of the 40th Design Automation Conference, 2003

Quasi-Static Scheduling for Concurrent Architectures.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

2002
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Design of Asynchronous Circuits Using Synchronous CAD Tools.
IEEE Design & Test of Computers, 2002

Design of Asynchronous Controllers with Delay Insensitive Interface.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Design of asynchronous circuits by synchronous CAD tools.
Proceedings of the 39th Design Automation Conference, 2002

Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Checking Delay-Insensitivity: 104 Gates and Beyond.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Quasi-Static Scheduling of Independent Tasksfor Reactive Systems.
Proceedings of the Applications and Theory of Petri Nets 2002, 2002

2000
Task generation and compile-time scheduling for mixed data-control embedded software.
Proceedings of the 37th Conference on Design Automation, 2000

Formal Verification of Safety Properties in Timed Circuits.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

Asynchronous Design Using Commercial HDL Synthesis Tools.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

Hardware and Petri Nets: Application to Asynchronous Circuit Design.
ICATPN, 2000

1999
Decomposition and technology mapping of speed-independent circuits using Boolean relations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

What is the cost of delay insensitivity?
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems.
Proceedings of the 36th Conference on Design Automation, 1999

Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Structural methods for the synthesis of speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Hazard-free implementation of speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Partial-scan delay fault testing of asynchronous circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems.
Journal of Circuits, Systems, and Computers, 1998

Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings.
Formal Methods in System Design, 1998

Lazy transition systems: application to timing optimization of asynchronous circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Asynchronous Interface Specification, Analysis and Synthesis.
Proceedings of the 35th Conference on Design Automation, 1998

Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.
Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998

1997
A region-based theory for state assignment in speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Partial scan delay fault testing of asynchronous circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Decomposition and technology mapping of speed-independent circuits using Boolean relations.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.
Proceedings of the European Design and Test Conference, 1997

Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

Coupling Asynchrony and Interrupts: Place Chart Nets.
Proceedings of the Application and Theory of Petri Nets 1997, 1997

1996
On the Models for Asynchronous Circuit Behaviour with OR Causality.
Formal Methods in System Design, 1996

Structural Methods for the Synthesis of Speed-Independent Circuits.
Proceedings of the 1996 European Design and Test Conference, 1996

Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis.
Proceedings of the 33st Conference on Design Automation, 1996

Complete state encoding based on the theory of regions.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings.
Proceedings of the Application and Theory of Petri Nets 1996, 1996

1995
Checking signal transition graph implementability by symbolic BDD traversal.
Proceedings of the 1995 European Design and Test Conference, 1995

On hazard-free implementation of speed-independent circuits.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Specification and analysis of self-timed circuits.
VLSI Signal Processing, 1994

Analysis and Identification of Speed-Independent Circuits on an Event Model.
Formal Methods in System Design, 1994

Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

Basic Gate Implementation of Speed-Independent Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

Verification of the speed-independent circuits by STG unfoldings.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

OR Causality: Modelling and Hardware Implementation.
Proceedings of the Application and Theory of Petri Nets 1994, 1994

1992
Analysis and Identification of Self-Timed Circuits.
Proceedings of the Designing Correct Circuits, 1992

1991
Formal method for self-timed design.
Proceedings of the conference on European design automation, 1991

1988
Signal Graphs: A Model for Designing Concurrent Logic.
Proceedings of the International Conference on Parallel Processing, 1988


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