Alexandre Yakovlev
Orcid: 0000-0003-0826-9330Affiliations:
- Newcastle University, Newcastle Upon Tyne, UK
According to our database1,
Alexandre Yakovlev
authored at least 379 papers
between 1985 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2017, "For contributions to theory and design of asynchronous circuits".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on zbmath.org
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on orcid.org
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on d-nb.info
On csauthors.net:
Bibliography
2024
IEEE ACM Trans. Comput. Biol. Bioinform., 2024
MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Bridging the Design Methodologies of Burst-Mode Specifications and Signal Transition Graphs.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2024
2023
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption.
Integr., November, 2023
IEEE Trans. Pattern Anal. Mach. Intell., September, 2023
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
A multi-step finite-state automaton for arbitrarily deterministic Tsetlin Machine learning.
Expert Syst. J. Knowl. Eng., May, 2023
Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification.
Microprocess. Microsystems, 2023
CoRR, 2023
CoRR, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Variable Duty Cycle Pulse Generation for Low Complexity Randomization in Machine Learning.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A Non-volatile State Retention Unit for Multi-storage Energy Management in Transient Systems.
Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Logic-Based Machine Learning with Reproducible Decision Model Using the Tsetlin Machine.
Proceedings of the 12th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Amplitude-Controlled Electromagnetic Pulse Switching Using Waveguide Junctions for High-Speed Computing Processes.
Adv. Intell. Syst., December, 2022
Trans. Petri Nets Other Model. Concurr., 2022
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.
IET Comput. Digit. Tech., 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022
Proceedings of the Forum on Specification & Design Languages, 2022
Runtime Energy Minimization of Distributed Many-Core Systems using Transfer Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 33rd International Conference on Concurrency Theory, 2022
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2022
2021
IEEE ACM Trans. Comput. Biol. Bioinform., 2021
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach.
Integr., 2021
QoS-Aware Power Minimization of Distributed Many-Core Servers using Transfer Q-Learning.
CoRR, 2021
Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
PLEDGER: Embedded Whole Genome Read Mapping using Algorithm-HW Co-design and Memory-aware Implementation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021
Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021
2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems.
IEEE Trans. Computers, 2020
IET Comput. Digit. Tech., 2020
A Novel Multi-step Finite-State Automaton for Arbitrarily Deterministic Tsetlin Machine Learning.
Proceedings of the Artificial Intelligence XXXVII, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020
Self-Amplifying Current-Mode Multiplier Design using a Multi-Memristor Crossbar Cell Structure.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
From Arithmetic to Logic based AI: A Comparative Analysis of Neural Networks and Tsetlin Machine.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133).
NII Shonan Meet. Rep., 2019
Integr., 2019
CoRR, 2019
Performance Analysis of MICS-Based RF Wireless Power Transfer System for Implantable Medical Devices.
IEEE Access, 2019
Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri Nets.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
A Pulse Width Modulation based Power-elastic and Robust Mixed-signal Perceptron Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 19th International Conference on Application of Concurrency to System Design, 2019
Proceedings of the Carl Adam Petri: Ideas, Personality, Impact, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects.
IEEE Trans. Emerg. Top. Comput., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 15th International Conference on Synthesis, 2018
Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous Systems.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Optogenetics in Silicon: A Neural Processor for Predicting Optically Active Neural Networks.
IEEE Trans. Biomed. Circuits Syst., 2017
Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the Software Engineering for Resilient Systems - 9th International Workshop, 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Proceedings of the New Generation of CAS, 2017
Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Ultra-Low Energy Data Driven Computing Using Asynchronous Micropipelines and Nano-Electro-Mechanical Relays.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Speedup and Parallelization Models for Energy-Efficient Many-Core Systems Using Performance Counters.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017
Proceedings of the 18th IEEE International Symposium on High Assurance Systems Engineering, 2017
Proceedings of the 2017 Forum on Specification and Design Languages, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Lifetime reliability characterization of N/MEMS used in power gating of digital integrated circuits.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Energy-efficient approximate multiplier design using bit significance-driven logic compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
Synthesis and optimization of asynchronous dual rail encoded circuits based on partial acknowledgement.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Selective Abstraction for Estimating Extra-Functional Properties in Networks-on-Chips Using ArchOn Framework.
Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017
Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017
2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Power-Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Challenges and opportunities in research and education of heterogeneous many-core applications.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Formal verification of clock domain crossing using gate-level models of metastable flip-flops.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the 15th International Conference on Modularity, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Int. J. Circuit Theory Appl., 2015
Fundam. Informaticae, 2015
Proceedings of the Software Engineering for Resilient Systems - 7th International Workshop, 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
Proceedings of the 15th International Conference on Application of Concurrency to System Design, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.
ACM Trans. Embed. Comput. Syst., 2014
IEEE Trans. Computers, 2014
IEEE Trans. Computers, 2014
Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Network on Chip optimization based on surrogate model assisted evolutionary algorithms.
Proceedings of the IEEE Congress on Evolutionary Computation, 2014
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
Studying the Interplay of Concurrency, Performance, Energy and Reliability with ArchOn - An Architecture-Open Resource-Driven Cross-Layer Modelling Framework.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014
2013
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems.
ACM Trans. Design Autom. Electr. Syst., 2013
IEEE Trans. Computers, 2013
IET Comput. Digit. Tech., 2013
IET Comput. Digit. Tech., 2013
IACR Cryptol. ePrint Arch., 2013
Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Comput. J., 2013
Proceedings of the 15th International Conference on Computer Modelling and Simulation, 2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2013
2012
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.
IEEE Trans. Parallel Distributed Syst., 2012
IET Comput. Digit. Tech., 2012
IET Comput. Digit. Tech., 2012
Proceedings of the 14th International Conference on Computer Modelling and Simulation, 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Proceedings of the 5th International Conference on New Technologies, 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
A scalable FPGA-based design for field programmable large-scale ion channel simulations.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication.
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
ACM J. Emerg. Technol. Comput. Syst., 2011
Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems.
IET Comput. Digit. Tech., 2011
IET Comput. Digit. Tech., 2011
IET Comput. Digit. Tech., 2011
M-PRES: a statistical tool for modelling the impact of manufacturing process variations on circuit-level performance parameters.
IET Circuits Devices Syst., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011
Proceedings of the Low Power Networks-on-Chip., 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Computers, 2010
Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator.
Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010
Performance improvement algorithms for colour image compression using DWT and multilevel block truncation coding.
Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010
Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design.
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010
Proceedings of the Workshops of the 31st International Conference on Application and Theory of Petri Nets and Other Models of Concurrency (PETRI NETS 2010) and of the 10th International Conference on Application of Concurrency to System Design (ACSD 2010), 2010
2009
IET Comput. Digit. Tech., 2009
Fine-grain stochastic modelling of dynamic power management policies and analysis of their power - latency tradeoffs.
IET Softw., 2009
Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits.
Proceedings of the ISMVL 2009, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
Proceedings of the Applications and Theory of Petri Nets, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels.
IEEE Trans. Computers, 2008
IEEE J. Solid State Circuits, 2008
Statistical modelling of the variation in advanced process technologies using a multi-level partitioned response.
IET Circuits Devices Syst., 2008
Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG Unfoldings.
Fundam. Informaticae, 2008
Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber.
Comput. J., 2008
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
High resolution flash time-to-digital converter with sub-picosecond measurement capabilities.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
FPGA Implementation of an Asynchronous Processor with Both Online and Offline Testing Capabilities.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
Proceedings of the Applications and Theory of Petri Nets, 29th International Conference, 2008
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Fundam. Informaticae, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007
2006
Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT.
Fundam. Informaticae, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
IEEE Trans. Computers, 2005
Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures.
Proceedings of the 2005 Design, 2005
Proceedings of the Advances in Databases and Information Systems, 2005
2004
IEEE Trans. Computers, 2004
Fundam. Informaticae, 2004
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the Integrated Circuit and System Design, 2004
MATLAB Models of ACMS in Control Systems.
Proceedings of the ICINCO 2004, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the Cryptographic Hardware and Embedded Systems, 2004
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004
2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003
Proceedings of the Lectures on Concurrency and Petri Nets, 2003
2002
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Visualization of Coding Conflicts in Asynchronous Circuit Design.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Synthesis of Asynchronous Circuits with Predictable Latency.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
Proceedings of the Applications and Theory of Petri Nets 2002, 2002
2001
Modelling and verification of an atomic action protocol implemented in Ada.
Comput. Syst. Sci. Eng., 2001
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Real Time Syst., 2000
Proceedings of the Integrated Circuit Design, 2000
On developing and verifying design abstractions for reliable concurrent programming in Ada.
Proceedings of the 10th International Workshop on Real-Time Ada, 2000
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
Proceedings of the Application and Theory of Petri Nets 2000, 2000
1999
Decomposition and technology mapping of speed-independent circuits using Boolean relations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
J. Syst. Archit., 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Int. J. Softw. Tools Technol. Transf., 1998
Formal Methods Syst. Des., 1998
Lazy transition systems: application to timing optimization of asynchronous circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the CONCUR '98: Concurrency Theory, 1998
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.
Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.
Proceedings of the European Design and Test Conference, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
Proceedings of the Application and Theory of Petri Nets 1997, 1997
1996
Integr., 1996
Formal Methods Syst. Des., 1996
Formal Methods Syst. Des., 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1995
IEEE Des. Test Comput., 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
Proceedings of the 31st Conference on Design Automation, 1994
Designing asynchronous circuits from behavioural specifications with internal conflicts.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994
Proceedings of the Application and Theory of Petri Nets 1994, 1994
1993
Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs.
Proceedings of the Sixth International Conference on VLSI Design, 1993
Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition Graphs.
Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993
1992
On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the Digest of Papers: FTCS-22, 1992
1989
A look at concurrency semantics through "lattice glasses".
Bull. EATCS, 1989
Analyzing Semantics of Concurrent Hardware Specifications.
Proceedings of the International Conference on Parallel Processing, 1989
1988
Signal Graphs: A Model for Designing Concurrent Logic.
Proceedings of the International Conference on Parallel Processing, 1988
1985
Signal Graphs: From Self-Timed to Timed Ones.
Proceedings of the International Workshop on Timed Petri Nets, 1985