Alexandre Yakovlev

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Amplitude-Controlled Electromagnetic Pulse Switching Using Waveguide Junctions for High-Speed Computing Processes.

[BibT_eX]

[DOI]

Ross Glyn MacDonald

Victor Pacheco-Peña

Adv. Intell. Syst., December, 2022

Practical Distributed Implementation of Very Large Scale Petri Net Simulations.

[BibT_eX]

[DOI]

Trans. Petri Nets Other Model. Concurr., 2022

Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2022

Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Editable asynchronous control logic for SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Automated Synthesis of Asynchronous Tsetlin Machines on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Non-deterministic event brokered computing.

[BibT_eX]

[DOI]

Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Formal Modelling of Burst-Mode Specifications in a Distributed Environment.

[BibT_eX]

[DOI]

Proceedings of the Forum on Specification & Design Languages, 2022

Runtime Energy Minimization of Distributed Many-Core Systems using Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Slimming down Petri Boxes: Compact Petri Net Models of Control Flows.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Concurrency Theory, 2022

Avoiding Exponential Explosion in Petri Net Models of Control Flows.

[BibT_eX]

[DOI]

Proceedings of the Application and Theory of Petri Nets and Concurrency, 2022

2021

Asynchrony and persistence in reaction systems.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2021

CORAL: Verification-Aware OpenCL Based Read Mapper for Heterogeneous Systems.

[BibT_eX]

[DOI]

Sidharth Maheshwari

Venkateshwarlu Y. Gudur

IEEE ACM Trans. Comput. Biol. Bioinform., 2021

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach.

[BibT_eX]

[DOI]

Integr., 2021

QoS-Aware Power Minimization of Distributed Many-Core Servers using Transfer Q-Learning.

[BibT_eX]

[DOI]

CoRR, 2021

Low-Power Audio Keyword Spotting using Tsetlin Machines.

[BibT_eX]

[DOI]

Ole-Christoffer Granmo

Fahim Kawsar

Akhil Mathur

CoRR, 2021

Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier Design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Low-Latency Asynchronous Logic Design for Inference at the Edge.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PLEDGER: Embedded Whole Genome Read Mapping using Algorithm-HW Co-design and Memory-aware Implementation.

[BibT_eX]

[DOI]

Venkateshwarlu Y. Gudur

Amit Acharyya

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Synthesis of SI Circuits from Burst-Mode Specifications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Self-timed Reinforcement Learning using Tsetlin Machine.

[BibT_eX]

[DOI]

Adrian Wheeldon

Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits.

[BibT_eX]

[DOI]

Moti Medina

Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

2020

Bootstrapped Driver and the Single-Event-Upset Effect.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Automating the Design of Asynchronous Logic Control for AMS Electronics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Advance Interconnect Circuit Modeling Design Using Fractional-Order Elements.

[BibT_eX]

[DOI]

Mohammed Al-daloo

Ahmed Soltan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Amdahl's law in the context of heterogeneous many-core systems - a survey.

[BibT_eX]

[DOI]

Kuruge Darshana Abeyrathna

IET Comput. Digit. Tech., 2020

A Novel Multi-step Finite-State Automaton for Arbitrarily Deterministic Tsetlin Machine Learning.

[BibT_eX]

[DOI]

Ole-Christoffer Granmo

Proceedings of the Artificial Intelligence XXXVII, 2020

Dynamics of Time-Domain Power-Elastic Circuits for Pervasive Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Explainability and Dependability Analysis of Learning Automata based AI Hardware.

[BibT_eX]

[DOI]

Adrian Wheeldon

Charalampos C. Tsimenidis

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Empirical Temperature Model of Self-Directed Channel Memristor.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020

Self-Amplifying Current-Mode Multiplier Design using a Multi-Memristor Crossbar Cell Structure.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

From Arithmetic to Logic based AI: A Comparative Analysis of Neural Networks and Tsetlin Machine.

[BibT_eX]

[DOI]

Ole-Christoffer Granmo

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

REPUTE: An OpenCL based Read Mapping Tool for Embedded Genomics.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Handshake Verification in WORKCRAFT.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019

Toward Designing Thermally-Aware Memristance Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133).

[BibT_eX]

[DOI]

NII Shonan Meet. Rep., 2019

Self-timed, minimum latency circuits for the internet of things.

[BibT_eX]

[DOI]

Integr., 2019

Ultra-low power <i>m</i>-sequence code generator for body sensor node applications.

[BibT_eX]

[DOI]

Ahmad N. Abdulfattah

Charalampos C. Tsimenidis

Integr., 2019

Neural Network Design for Energy-Autonomous AI Applications using Temporal Encoding.

[BibT_eX]

[DOI]

CoRR, 2019

Performance Analysis of MICS-Based RF Wireless Power Transfer System for Implantable Medical Devices.

[BibT_eX]

[DOI]

Ahmad N. Abdulfattah

Bessam Z. Al-Jewad

IEEE Access, 2019

Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

A Pulse Width Modulation based Power-elastic and Robust Mixed-signal Perceptron Design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Generalised Asynchronous Arbiter.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Application of Concurrency to System Design, 2019

Living Lattices.

[BibT_eX]

[DOI]

Proceedings of the Carl Adam Petri: Ideas, Personality, Impact, 2019

2018

Speedup and Power Scaling Models for Heterogeneous Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2018

High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Real-Power Computing.

[BibT_eX]

[DOI]

Shidhartha Das

IEEE Trans. Computers, 2018

Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Modelling Switched-Capacitor DC-DC Converters with Signal Transition Graphs.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous Systems.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Overview study of on-chip interconnect modelling approaches and its trend.

[BibT_eX]

[DOI]

Mohammed Al-daloo

Ahmed Soltan

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

An Excitation Time Model for General-purpose Memristance Tuning Circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Verification of Speed-Independent Circuits with Arbitration in Workcraft.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

Loadable Kessels Counter.

[BibT_eX]

[DOI]

Oyinkuro Benafa

Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017

A Resilient 2-D Waveguide Communication Fabric for Hybrid Wired-Wireless NoC Design.

[BibT_eX]

[DOI]

Michael Opoku Agyeman

IEEE Trans. Parallel Distributed Syst., 2017

A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Optogenetics in Silicon: A Neural Processor for Predicting Optically Active Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2017

Voltage, Throughput, Power, Reliability, and Multicore Scaling.

[BibT_eX]

[DOI]

Ali Aalsaud

James J. Davis

Joshua M. Levine

Sheng Yang

Computer, 2017

Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Modelling for Systems with Holistic Fault Tolerance.

[BibT_eX]

[DOI]

Proceedings of the Software Engineering for Resilient Systems - 9th International Workshop, 2017

Power proportional adder design for Internet of Things in a 65 nm process.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Pulse controlled memristor-based delay element.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Approximate adder segmentation technique and significance-driven error correction.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Asynchronous Arbitration Primitives for New Generation of Circuits and Systems.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Ultra-Low Energy Data Driven Computing Using Asynchronous Micropipelines and Nano-Electro-Mechanical Relays.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Speedup and Parallelization Models for Energy-Efficient Many-Core Systems Using Performance Counters.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Programming Model to Develop Supercomputer Combinatorial Solvers.

[BibT_eX]

[DOI]

Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

Architecting Holistic Fault Tolerance.

[BibT_eX]

[DOI]

Alessandro F. Garcia

Proceedings of the 18th IEEE International Symposium on High Assurance Systems Engineering, 2017

Language and Hardware Acceleration Backend for Graph Processing.

[BibT_eX]

[DOI]

Alessandro de Gennaro

Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017

Elmore delay in the fractional order domain.

[BibT_eX]

[DOI]

Ahmed Soltan

Ahmed G. Radwan

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Self-timed control of multiphase switched capacitor converters.

[BibT_eX]

[DOI]

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Multiphase ternary Fibonacci 2D switched capacitor converters.

[BibT_eX]

[DOI]

Tsorng-Juu Peter Liang

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Lifetime reliability characterization of N/MEMS used in power gating of digital integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Benefits of asynchronous control for analog electronics: Multiphase buck case study.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy-efficient approximate multiplier design using bit significance-driven logic compression.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

WAITX: An Arbiter for Non-persistent Signals.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity.

[BibT_eX]

[DOI]

Johnson Fernandes

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Synthesis and optimization of asynchronous dual rail encoded circuits based on partial acknowledgement.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Selective Abstraction for Estimating Extra-Functional Properties in Networks-on-Chips Using ArchOn Framework.

[BibT_eX]

[DOI]

Alexei Iliasov

Charalampos C. Tsimenidis

Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017

Formal Design and Verification of an Asynchronous SRAM Controller.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017

2016

Design of Mixed-Signal Systems With Asynchronous Control.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Subthreshold-based m-sequence code generator for ultra low-power body sensor nodes.

[BibT_eX]

[DOI]

Ahmad N. Abdulfattah

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

A fixed window Level Crossing ADC with activity dependent power dissipation.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Power-Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

MEMS-based power delivery control for bursty applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A smart all-digital charge to digital converter.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Stacking voltage-controlled oscillators: Analysis and application.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Energy efficient bootstrapped CMOS inverter for ultra-low power applications.

[BibT_eX]

[DOI]

Mohammed Al-daloo

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Challenges and opportunities in research and education of heterogeneous many-core applications.

[BibT_eX]

[DOI]

Dave Burke

Proceedings of the 11th European Workshop on Microelectronics Education, 2016

Low power voltage sensing through capacitance to digital conversion.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Formal verification of clock domain crossing using gate-level models of metastable flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fast capacitance-to-digital converter with internal reference.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

On structuring holistic fault tolerance.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Modularity, 2016

2015

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging.

[BibT_eX]

[DOI]

James Sebastian Guido

IEEE Trans. Very Large Scale Integr. Syst., 2015

On hyperbolic laws of capacitor discharge through self-timed digital loads.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2015

Persistent and Nonviolent Steps and the Design of GALS Systems.

[BibT_eX]

[DOI]

Johnson Fernandes

Lukasz Mikulski

Fundam. Informaticae, 2015

Engineering Cross-Layer Fault Tolerance in Many-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the Software Engineering for Resilient Systems - 7th International Workshop, 2015

A Formal Specification and Prototyping Language for Multi-core System Management.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Wideband dynamic voltage sensing mechanism for EH systems.

[BibT_eX]

[DOI]

Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design.

[BibT_eX]

[DOI]

Michael Opoku Agyeman

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

An elastic timer for wide dynamic working range.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Compositional design of asynchronous circuits from behavioural concepts.

[BibT_eX]

[DOI]

Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures.

[BibT_eX]

[DOI]

Michael Opoku Agyeman

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

A least squares method applied to multiphase switched capacitor converters.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

GALS synthesis and verification for xMAS models.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Design and Verification of Speed-Independent Multiphase Buck Controller.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Opportunistic Merge Element.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Order Graphs and Cross-Layer Parametric Significance-Driven Modelling.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Application of Concurrency to System Design, 2015

2014

Eliminating Synchronization Latency Using Sequenced Latching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Synthesis of Processor Instruction Sets from High-Level ISA Specifications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

A scalable physical model for Nano-Electro-Mechanical relays.

[BibT_eX]

[DOI]

Haider Alrudainy

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Asynchronously assisted FPGA for variability.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Asynchronous design for new on-chip wide dynamic range power electronics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

ArchOn: Architecture-open Resource-driven Cross-layer Modelling Framework.

[BibT_eX]

[DOI]

Alexei Iliasov

Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Network on Chip optimization based on surrogate model assisted evolutionary algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2014

GALS Partitioning by Behavioural Decoupling Expressed in Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

Studying the Interplay of Concurrency, Performance, Energy and Reliability with ArchOn - An Architecture-Open Resource-Driven Cross-Layer Modelling Framework.

[BibT_eX]

[DOI]

Alexei Iliasov

Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013

Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Concurrent Multiresource Arbiter: Design and Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Hybrid wire-surface wave interconnects for next-generation networks-on-chip.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2013

Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2013

Power Balanced Circuits for Leakage-Power-Attacks Resilient Design.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip.

[BibT_eX]

[DOI]

Comput. J., 2013

Simulation Testing of a Real-Time Heuristic Scheduler with Automotive Benchmarks.

[BibT_eX]

[DOI]

James Docherty

Proceedings of the 15th International Conference on Computer Modelling and Simulation, 2013

Variability analysis of self-timed SRAM robustness.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Wide-range, reference free, on-chip voltage sensor for variable Vdd operations.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Towards reliable hybrid bio-silicon integration using novel adaptive control system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools.

[BibT_eX]

[DOI]

Pascal Vivet

Marc Renaudin

Proceedings of the Design, Automation and Test in Europe, 2013

Capacitor Discharging Through Asynchronous Circuit Switching.

[BibT_eX]

[DOI]

Reza Ramezani

Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

Design-for-adaptivity of microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Step Persistence in the Design of GALS Systems.

[BibT_eX]

[DOI]

Johnson Fernandes

Proceedings of the Application and Theory of Petri Nets and Concurrency, 2013

2012

Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Mixed Radix Reed-Muller Expansions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Towards power-elastic systems through concurrency management.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Design and security evaluation of balanced 1-of-n circuits.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Identification of Key Energy Harvesting Parameters through Monte Carlo Simulations.

[BibT_eX]

[DOI]

James Docherty

Proceedings of the 14th International Conference on Computer Modelling and Simulation, 2012

Adaptive Synchronization for DVFS Applications.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Self-Timed Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on New Technologies, 2012

A hybrid power delivery method for asynchronous loads in energy harvesting systems.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Developing survival instincts in computing systems.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Surface wave communication system for on-chip and off-chip interconnects.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Ultra-low power transmitter.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Error detection and correction of single event upset (SEU) tolerant latch.

[BibT_eX]

[DOI]

Norhuzaimin Julai

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

An RTL method for hiding clock domain crossing latency.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Intra-chip physical parameter sensor for FPGAS using flip-flop metastability.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A scalable FPGA-based design for field programmable large-scale ion channel simulations.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

VARMA - VARiability modelling and analysis tool.

[BibT_eX]

[DOI]

Gordon Russell

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier.

[BibT_eX]

[DOI]

Ahmed Naif M. Alahmadi

Gordon Russell

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Minimizing power supply noise through harmonic mappings in networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

On Dual-Rail Control Logic for Enhanced Circuit Robustness.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

Algebra of Parameterised Graphs.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2011

Security Evaluation of Balanced 1-of- n Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Sub-threshold synchronizer.

[BibT_eX]

[DOI]

Microelectron. J., 2011

Self-Timed SRAM for Energy Harvesting Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2011

A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2011

Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems.

[BibT_eX]

[DOI]

Ken S. Stevens

IET Comput. Digit. Tech., 2011

Encoding of processor instruction sets with explicit concurrency control.

[BibT_eX]

[DOI]

Arseniy Alekseyev

IET Comput. Digit. Tech., 2011

Statistical analysis of crosstalk-induced errors for on-chip interconnects.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

M-PRES: a statistical tool for modelling the impact of manufacturing process variations on circuit-level performance parameters.

[BibT_eX]

[DOI]

Santosh Shedabale

Gordon Russell

IET Circuits Devices Syst., 2011

Flat Arbiters.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2011

Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Communication centric on-chip power grid models for networks-on-chip.

[BibT_eX]

[DOI]

Nizar Dahir

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Power adaptive computing system design in energy harvesting environment.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

On-chip dynamic programming networks using 3D-TSV integration.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Improving the Robustness of Self-timed SRAM to Variable Vdds.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Formal modelling and transformations of processor instruction sets.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Reconfigurable controllers for synchronization via wagging.

[BibT_eX]

[DOI]

James Sebastian Guido

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Variation tolerant asynchronous FPGA (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Memory efficient on-line streaming for multichannel spike train analysis.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Towards neuro-silicon interface using reconfigurable dynamic clamping.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Energy-modulated computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Redressing timing issues for speed-independent circuits in deep submicron age.

[BibT_eX]

[DOI]

Yu Li

Proceedings of the Design, Automation and Test in Europe, 2011

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Variation Tolerant AFPGA Architecture.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems.

[BibT_eX]

[DOI]

Yu Zhou

Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

Improved Parallel Composition of Labelled Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

Asynchronous Communications for NoCs.

[BibT_eX]

[DOI]

Stanislavs Golubcovs

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Conditional Partial Order Graphs: Model, Synthesis, and Application.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator.

[BibT_eX]

[DOI]

Sami Hasan

Said Boussakta

Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010

Secure Design Flow for Asynchronous Multi-valued Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Highly parallel multi-resource arbiters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Asynchronous FPGA architecture with distributed control.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Stochastic analysis of power, latency and the degree of concurrency.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Asynchronous design, Quo Vadis?

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator.

[BibT_eX]

[DOI]

Sami Hasan

Said Boussakta

Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010

Performance improvement algorithms for colour image compression using DWT and multilevel block truncation coding.

[BibT_eX]

[DOI]

Saad Al-Azawi

Said Boussakta

Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010

Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design.

[BibT_eX]

[DOI]

Arseniy Alekseyev

Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010

Introduction.

[BibT_eX]

[DOI]

Jörg Desel

Proceedings of the Workshops of the 31st International Conference on Application and Theory of Petri Nets and Other Models of Concurrency (PETRI NETS 2010) and of the 10th International Conference on Application of Concurrency to System Design (ACSD 2010), 2010

2009

Efficient advanced encryption standard implementation using lookup and normal basis.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Fine-grain stochastic modelling of dynamic power management policies and analysis of their power - latency tradeoffs.

[BibT_eX]

[DOI]

IET Softw., 2009

Synthesis of Nets with Step Firing Policies.

[BibT_eX]

[DOI]

Philippe Darondeau

Fundam. Informaticae, 2009

Desynchronisation Technique Using Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009

The Magic Rule of Tiles: Virtual Delay Insensitivity.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Connection-centric network for spiking neural networks.

[BibT_eX]

[DOI]

Robin Emery

E. Graeme Chester

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits.

[BibT_eX]

[DOI]

Proceedings of the ISMVL 2009, 2009

On the trade-off between resolution time and delay times in bistable circuits.

[BibT_eX]

[DOI]

Mohammed Alshaikh

David Kinniment

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Synthesis of Multiple Rail Phase Encoding Circuits.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

Modular Approach to Multi-resource Arbiter Design.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

Workcraft - A Framework for Interpreted Graph Models.

[BibT_eX]

[DOI]

Ivan Poliakov

Proceedings of the Applications and Theory of Petri Nets, 2009

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs.

[BibT_eX]

[DOI]

Panagiotis Asimakopoulos

Geert Van der Plas

Paul Marchal

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

Phase-Encoding for On-Chip Signalling.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

On-Chip Measurement of Deep Metastability in Synchronizers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

Statistical modelling of the variation in advanced process technologies using a multi-level partitioned response.

[BibT_eX]

[DOI]

Sanatan Chattopadhyay

IET Circuits Devices Syst., 2008

Analysis of Static Data Flow Structures.

[BibT_eX]

[DOI]

Ivan Poliakov

Fundam. Informaticae, 2008

Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG Unfoldings.

[BibT_eX]

[DOI]

Agnes Madalinski

Fundam. Informaticae, 2008

Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber.

[BibT_eX]

[DOI]

Peter Y. K. Cheung

Comput. J., 2008

Global interconnections in FPGAs: modeling and performance analysis.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Implementation of Wave-Pipelined Interconnects in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

High resolution flash time-to-digital converter with sub-picosecond measurement capabilities.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Conversion driven design of binary to mixed radix circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Implementation of a phase-encoding signalling prototype chip.

[BibT_eX]

[DOI]

Alex Bystrov

Proceedings of the ESSCIRC 2008, 2008

Serialized Asynchronous Links for NoC.

[BibT_eX]

[DOI]

Luca Benini

Proceedings of the Design, Automation and Test in Europe, 2008

Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Asynchronous transient resilient links for NoC.

[BibT_eX]

[DOI]

Simon Ogg

Bashir M. Al-Hashimi

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Adapting Synchronizers to the Effects of on Chip Variability.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

Automated Verification of Asynchronous Circuits Using Circuit Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

FPGA Implementation of an Asynchronous Processor with Both Online and Offline Testing Capabilities.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

A Symbolic Algorithm for the Synthesis of Bounded Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the Applications and Theory of Petri Nets, 29th International Conference, 2008

Verification of conditional partial order graphs.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008

2007

Registers for Phase Difference Based Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Measuring Deep Metastability and Its Effect on Synchronizer Performance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Direct Mapping of Low-Latency Asynchronous Controllers From STGs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Automating Synthesis of Asynchronous Communication Mechanisms.

[BibT_eX]

[DOI]

Kyller Costa Gorgônio

Jordi Cortadella

Fundam. Informaticae, 2007

Asynchronous Functional Coupling for Low Power Sensor Network Processors.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.

[BibT_eX]

[DOI]

Simon Ogg

Enrico Valli

Bashir M. Al-Hashimi

Luca Benini

Proceedings of the First International Symposium on Networks-on-Chips, 2007

NoC Communication Strategies Using Time-to-Digital Conversion.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Asynchronous links for nanonets.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Impact of strain on the design of low-power high-speed circuits.

[BibT_eX]

[DOI]

Hiran Ramakrishnan

Koushik Maharatna

Sanatan Chattopadhyay

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits.

[BibT_eX]

[DOI]

K. T. Gardiner

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Delay/Phase Regeneration Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

Asynchronous Data Path Models.

[BibT_eX]

[DOI]

Ivan Poliakov

Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

The Design of Virtual Self-timed Block for Activity Communication in SOC.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006

Buffered Asynchronous Communication Mechanisms.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2006

Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2006

A Robust Synchronizer.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Modeling And Performance Analysis of GALS architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

Virtual self-timed blocks for systems-on-chip.

[BibT_eX]

[DOI]

Yuan Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Online Testing by Protocol Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Cost-aware synthesis of asynchronous circuits based on partial acknowledgement.

[BibT_eX]

[DOI]

Yu Zhou

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Low-Cost Online Testing of Asynchronous Handshakes.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

Multiple-Rail Phase-Encoding for NoC.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005

Design and Analysis of Dual-Rail Circuits for Security Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits.

[BibT_eX]

[DOI]

Dumitru Potop-Butucaru

Benoît Caillaud

Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

Off-Line Testing of Asynchronous Circuits.

[BibT_eX]

[DOI]

Deepali Koppad

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

PSK Signalling on NoC Buses.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

On-Line Testing of Globally Asynchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Power-Balanced Self Checking Circuits for Cryptographic Chips.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Power-balanced asynchronous logic.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

A Multi-version Data Model and Semantic-Based Transaction Processing Protocol.

[BibT_eX]

[DOI]

Proceedings of the Advances in Databases and Information Systems, 2005

2004

Design and Analysis of a Self-Timed Duplex Communication System.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Detecting State Encoding Conflicts in STG Unfoldings Using SAT.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2004

A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Low Latency Synchronization Through Speculation.

[BibT_eX]

[DOI]

D. J. Kinniment

Proceedings of the Integrated Circuit and System Design, 2004

MATLAB Models of ACMS in Control Systems.

[BibT_eX]

Proceedings of the ICINCO 2004, 2004

An Asynchronous Synthesis Toolset Using Verilog.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Improving the Security of Dual-Rail Circuits.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2004

Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

2003

On-chip structures for timing measurement and test.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2003

STG Optimisation in the Direct Mapping of Asynchronous Circuits .

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Monotonic Circuits with Complete Acknowledgement.

[BibT_eX]

[DOI]

Nikolai Starodoubtsev

Sergei Bystrov

Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

Low-Latency Contro Structures with Slack.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

Detecting State Coding Conflicts in STG Unfoldings Using SAT.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

Synthesis of Asynchronous Hardware from Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the Lectures on Concurrency and Petri Nets, 2003

2002

Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Data Communication in Systems with Heterogeneous Timing.

[BibT_eX]

[DOI]

IEEE Micro, 2002

Synchronization circuit performance.

[BibT_eX]

[DOI]

David J. Kinniment

IEEE J. Solid State Circuits, 2002

Design of Asynchronous Controllers with Delay Insensitive Interface.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Logic Design of Asynchronous Circuits (Tutorial Abstract).

[BibT_eX]

[DOI]

Jordi Cortadella

Jim D. Garside

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Visualization of Coding Conflicts in Asynchronous Circuit Design.

[BibT_eX]

Agnes Madalinski

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Synthesis of Asynchronous Circuits with Predictable Latency.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Asynchronous circuit synthesis via direct translation.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of the oscillation problem in tri-flops.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Detecting State Coding Conflicts in STGs Using Integer Programming.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Visualization of Partial Order Models in VLSI Design Flow.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

On-Chip Structures for Timing Measurements and Test.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Is the Die Cast for the Token Game?

[BibT_eX]

[DOI]

Proceedings of the Applications and Theory of Petri Nets 2002, 2002

2001

Modelling and verification of an atomic action protocol implemented in Ada.

[BibT_eX]

Comput. Syst. Sci. Eng., 2001

Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000

Synchronous and asynchronous A-D conversion.

[BibT_eX]

[DOI]

David Kinniment

B. Gao

IEEE Trans. Very Large Scale Integr. Syst., 2000

WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets.

[BibT_eX]

[DOI]

Albert Koelmans

Real Time Syst., 2000

Semi-modular Latch Chains for Asynchronous Circuit Design.

[BibT_eX]

[DOI]

Nikolai Starodoubtsev

Proceedings of the Integrated Circuit Design, 2000

On developing and verifying design abstractions for reliable concurrent programming in Ada.

[BibT_eX]

[DOI]

Proceedings of the 10th International Workshop on Real-Time Ada, 2000

Asynchronous Communication Mechanisms Using Self-Timed Circuits.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

Priority Arbiters.

[BibT_eX]

[DOI]

D. J. Kinniment

Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

Hardware and Petri Nets: Application to Asynchronous Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the Application and Theory of Petri Nets 2000, 2000

1999

Decomposition and technology mapping of speed-independent circuits using Boolean relations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Logic decomposition of speed-independent circuits.

[BibT_eX]

[DOI]

Proc. IEEE, 1999

Asynchronous microprocessors: From high level model to FPGA implementation.

[BibT_eX]

[DOI]

J. Syst. Archit., 1999

What is the cost of delay insensitivity?

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Hazard-free implementation of speed-independent circuits.

[BibT_eX]

[DOI]

Alex Kondratyev

Michael Kishinevsky

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Deriving Petri Nets for Finite Transition Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Analysing Superscalar Processor Architectures with Coloured Petri Nets.

[BibT_eX]

[DOI]

Albert Koelmans

Int. J. Softw. Tools Technol. Transf., 1998

Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1998

Lazy transition systems: application to timing optimization of asynchronous circuits.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Unfolding and Finite Prefix for Nets with Read Arcs.

[BibT_eX]

[DOI]

Walter Vogler

Alexei L. Semenov

Proceedings of the CONCUR '98: Concurrency Theory, 1998

Towards Asynchronous A-D Conversion.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.

[BibT_eX]

[DOI]

Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998

1997

A region-based theory for state assignment in speed-independent circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Designing an asynchronous processor using Petri nets.

[BibT_eX]

[DOI]

IEEE Micro, 1997

Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Synthesis of Speed-Independent Circuits from STG-Unfolding Segment.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

Partial order based approach to synthesis of speed-independent circuits.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

Coupling Asynchrony and Interrupts: Place Chart Nets.

[BibT_eX]

[DOI]

Proceedings of the Application and Theory of Petri Nets 1997, 1997

1996

Modelling, analysis and synthesis of asynchronous control circuits using Petri nets.

[BibT_eX]

[DOI]

Integr., 1996

A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis.

[BibT_eX]

[DOI]

Alberto L. Sangiovanni-Vincentelli

Luciano Lavagno

Formal Methods Syst. Des., 1996

On the Models for Asynchronous Circuit Behaviour with OR Causality.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1996

Verification of asynchronous circuits using Time Petri Net unfolding.

[BibT_eX]

[DOI]

Alexei L. Semenov

Proceedings of the 33st Conference on Design Automation, 1996

Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

Complete state encoding based on the theory of regions.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995

High-Level Modeling and Design of Asynchronous Interface Logic.

[BibT_eX]

[DOI]

Albert Koelmans

Luciano Lavagno

IEEE Des. Test Comput., 1995

Synthesizing Petri nets from state-based models.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Checking signal transition graph implementability by symbolic BDD traversal.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Designing an asynchronous pipeline token ring interface.

[BibT_eX]

[DOI]

Victor Varshavsky

Vyacheslav Marakhovsky

Alexei L. Semenov

Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994

A low latency asynchronous arbitration circuit.

[BibT_eX]

[DOI]

A. Petrov

Luciano Lavagno

IEEE Trans. Very Large Scale Integr. Syst., 1994

Basic Gate Implementation of Speed-Independent Circuits.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

Designing asynchronous circuits from behavioural specifications with internal conflicts.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

OR Causality: Modelling and Hardware Implementation.

[BibT_eX]

[DOI]

Proceedings of the Application and Theory of Petri Nets 1994, 1994

1993

Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition Graphs.

[BibT_eX]

A. I. Petrov

Leonid Ya. Rosenblum

Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993

1992

On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

A Structural Technique For Fault-Protection in Asynchronous Interfaces.

[BibT_eX]

[DOI]