Marius Meyer
Orcid: 0000-0002-5612-5414
According to our database1,
Marius Meyer
authored at least 6 papers
between 2020 and 2024.
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Bibliography
2024
Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL.
CoRR, 2024
2023
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks.
ACM Trans. Reconfigurable Technol. Syst., June, 2023
2022
In-depth FPGA accelerator performance evaluation with single node benchmarks from the HPC challenge benchmark suite for Intel and Xilinx FPGAs using OpenCL.
J. Parallel Distributed Comput., 2022
2021
Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks.
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021
2020
Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite.
CoRR, 2020
Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.
Proceedings of the 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2020