Christian Plessl

Orcid: 0000-0001-5728-9982

Affiliations:
  • University of Paderborn, Paderborn Center for Parallel Computing (PC^2), Germany
  • ETH Zurich, Computer Engineering and Networks Laboratory, Switzerland (PhD 2006)


According to our database1, Christian Plessl authored at least 103 papers between 2002 and 2024.

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Bibliography

2024
Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL.
CoRR, 2024

2023
Breaking the exascale barrier for the electronic structure problem in <i>ab-initio</i> molecular dynamics.
Int. J. High Perform. Comput. Appl., September, 2023

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

A Two-Step Machine Learning Method for Predicting the Formation Energy of Ternary Compounds.
Comput., May, 2023

A computation of D(9) using FPGA Supercomputing.
CoRR, 2023

Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline.
Proceedings of the High Performance Computing - 38th International Conference, 2023

Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes.
Proceedings of the Platform for Advanced Scientific Computing Conference, 2023

Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation.
Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

Computing and Compressing Electron Repulsion Integrals on FPGAs.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations.
ACM Trans. Reconfigurable Technol. Syst., 2022

Towards electronic structure-based <i>ab-initio</i> molecular dynamics simulations with hundreds of millions of atoms.
Parallel Comput., 2022

In-depth FPGA accelerator performance evaluation with single node benchmarks from the HPC challenge benchmark suite for Intel and Xilinx FPGAs using OpenCL.
J. Parallel Distributed Comput., 2022

CP2K on the road to exascale.
CoRR, 2022

The HighPerMeshes framework for numerical algorithms on unstructured grids.
Concurr. Comput. Pract. Exp., 2022

A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges.
Proceedings of the HPC Asia 2022: International Conference on High Performance Computing in Asia-Pacific Region, Virtual Event, Japan, January 12, 2022

2021
High Level Synthesis Implementation of a Three-dimensional Systolic Array Architecture for Matrix Multiplications on Intel Stratix 10 FPGAs.
CoRR, 2021

A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays.
CoRR, 2021

Enabling Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.
CoRR, 2021

High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
High-Performance Spectral Element Methods on Field-Programmable Gate Arrays.
CoRR, 2020

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite.
CoRR, 2020

Accurate Sampling with Noisy Forces from Approximate Computing.
Comput., 2020

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.
Proceedings of the 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2020

A submatrix-based method for approximate matrix function evaluation in the quantum chemistry code CP2K.
Proceedings of the International Conference for High Performance Computing, 2020

Efficient Ab-Initio Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids.
Proceedings of the Euro-Par 2020: Parallel Processing Workshops, 2020

2019
Transparent Acceleration for Heterogeneous Platforms With Compilation to OpenCL.
ACM Trans. Archit. Code Optim., 2019

FPGAs im Rechenzentrum.
Inform. Spektrum, 2019

OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
Using Approximate Computing for the Calculation of Inverse Matrix <i>p</i>th Roots.
IEEE Embed. Syst. Lett., 2018

Automated code acceleration targeting heterogeneous openCL devices.
Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2018

A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices.
Proceedings of the Platform for Advanced Scientific Computing Conference, 2018

OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.
ACM Trans. Reconfigurable Technol. Syst., 2017

A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices.
CoRR, 2017

Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots.
CoRR, 2017

Foreword to the special issue of the 18th IEEE international conference on computational science and engineering (CSE2015).
Concurr. Comput. Pract. Exp., 2017

Flexible FPGA design for FDTD using OpenCL.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Self-aware Compute Nodes.
Proceedings of the Self-aware Computing Systems - An Engineering Approach, 2016

Potential and methods for embedding dynamic offloading decisions into application code.
Comput. Electr. Eng., 2016

Using just-in-time code generation for transparent resource management in heterogeneous systems.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

ReconOS.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Approximate Computing.
Inform. Spektrum, 2015

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study.
Int. J. Reconfigurable Comput., 2015

Self-Aware and Self-Expressive Systems.
Computer, 2015

Transparent offloading of computational hotspots from binary code to Xeon Phi.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.
ACM Trans. Reconfigurable Technol. Syst., 2014

ReconOS: An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 2014

Seven recipes for setting your FPGA on fire - A cookbook on heat generators.
Microprocess. Microsystems, 2014

Easy-to-Use On-the-Fly Binary Program Acceleration on Many-Cores.
CoRR, 2014

Deferring accelerator offloading decisions to application runtime.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Kernel-centric acceleration of high accuracy stereo-matching.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Reconstructing AES Key Schedules from Decayed Memory with FPGAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Accelerating finite difference time domain simulations with reconfigurable dataflow computers.
SIGARCH Comput. Archit. News, 2013

On-The-Fly Computing: A novel paradigm for individualized IT services.
Proceedings of the 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013

Parallel Macro Pipelining on the Intel SCC Many-Core Computer.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

FPGA-accelerated key search for cold-boot attacks against AES.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
IMORC: An infrastructure and architecture template for implementing high-performance reconfigurable FPGA accelerators.
Microprocess. Microsystems, 2012

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.
Int. J. Reconfigurable Comput., 2012

Pragma based parallelization - Trading hardware efficiency for ease of use?
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Eight ways to put your FPGA on fire - A systematic study of heat generators.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Turning control flow graphs into function calls: Code generation for heterogeneous architectures.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

Exploration of ring oscillator design space for temperature measurements on FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Convey vector personalities - FPGA acceleration with an openmp-like programming effort?
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.
Int. J. Reconfigurable Comput., 2011

Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Just-in-Time Instruction Set Extension - Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Performance estimation framework for automated exploration of CPU-accelerator architectures.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Pruning the Design Space for Just-in-Time Processor Customization.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Rupeas: Ruby powered event analysis DSL.
Proceedings of the Seventh International Conference on Networked Sensing Systems, 2010

Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

An Open Source Circuit Library with Benchmarking Facilities.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Configurable Processor Architectures: History and Trends.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware accelerators.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Demo abstract: Operating a sensor network at 3500 m above sea level.
Proceedings of the 8th International Conference on Information Processing in Sensor Networks, 2009

PermaDAQ: A scientific instrument for precision sensing and data recovery in environmental extremes.
Proceedings of the 8th International Conference on Information Processing in Sensor Networks, 2009

An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.
Proceedings of the FCCM 2009, 2009

Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

EvoCaches: Application-specific Adaptation of Cache Mappings.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.
Proceedings of the IEEE International Conference on Sensor Networks, 2008

A Hardware Accelerator for k-th Nearest Neighbor Thinning.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007
Increasing the reliability of wireless sensor networks with a distributed testing framework.
Proceedings of the 4th Workshop on Embedded Networked Sensors, 2007

2006
Hardware virtualization on a coarse-grained reconfigurable processor.
PhD thesis, 2006

Optimal temporal partitioning based on slowdown and retiming.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005
System-level performance evaluation of reconfigurable processors.
Microprocess. Microsystems, 2005

Zippy - A coarse-grained reconfigurable array with support for hardware virtualization.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Virtualization of Hardware - Introduction and Survey.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003
Instance-Specific Accelerators for Minimum Covering.
J. Supercomput., 2003

The case for reconfigurable hardware in wearable computing.
Pers. Ubiquitous Comput., 2003

TKDM - a reconfigurable co-processor in a PC's memory slot.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Virtualizing Hardware with Multi-context Reconfigurable Arrays.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Co-Simulation of a Hybrid Multi-Context Architecture.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
Reconfigurable Hardware in Wearable Computing Nodes.
Proceedings of the 6th International Symposium on Wearable Computers (ISWC 2002), 2002

Partially Reconfigurable Cores for Xilinx Virtex.
Proceedings of the Field-Programmable Logic and Applications, 2002

Custom Computing Machines for the Set Covering Problem.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002


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