Markus Weinhardt

According to our database1, Markus Weinhardt authored at least 28 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
An Analysis of Mapping Polybench Kernels to HPC CGRAs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021
HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2019
High-Level Synthesis Oriented Restructuring of Functions with While Loops.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Using Template Metaprogramming for Hardware Description.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018

2016
Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

High-Level Synthesis.
Proceedings of the FPGAs for Software Programmers, 2016

2015
SAccO: An implementation platform for scalable FPGA accelerators.
Microprocess. Microsystems, 2015

2014
High-Level Design of Portable and Scalable FPGA Accelerators.
CoRR, 2014

2013
A framework for PC applications with portable and scalable FPGA accelerators.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2012
Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Dynamic Reconfiguration for Irregular Code Using FNC-PAE Processor Cores.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Compiling for reconfigurable computing: A survey.
ACM Comput. Surv., 2010

2004
Using function folding to improve silicon efficiency of reconfigurable arithmetic arrays.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2003
PACT XPP - A Self-Reconfigurable Data Processing Architecture.
J. Supercomput., 2003

From C Programs to the Configure-Execute Model.
Proceedings of the 2003 Design, 2003

2002
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture.
Proceedings of the Field-Programmable Logic and Applications, 2002

Fast and Guaranteed C Compilation onto the PACT-XPP? Reconfigurable Computing Platform.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Pipeline vectorization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Task-Parallel Programming of Reconfigurable Systems.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Evaluating Hardware Compilation Techniques.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Memory Access Optimization and RAM Inference for Pipeline Vectorization.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Pipeline Vectorization for Reconfigurable Systems.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1997
Übersetzungsmethoden für strukturprogrammierbare Rechner.
PhD thesis, 1997

1996
Computing Weight Distributions of Binary Linear Block Codes on a CCM.
Proceedings of the Field-Programmable Logic, 1996

Portable Pipeline Synthesis for FCCMs.
Proceedings of the Field-Programmable Logic, 1996

1995
Integer Programming for Partitioning in Software Oriented Codesign.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995


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