Christian Hochberger

According to our database1, Christian Hochberger authored at least 62 papers between 1995 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Bibliography

2018
AMIDAR Project: Lessons Learned in 15 Years of Researching Adaptive Processors.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Online analysis of debug trace data for embedded systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Fast DSE for Automated Parallelization of Embedded Legacy Applications.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems.
Proceedings of the Formal Methods: Foundations and Applications - 20th Brazilian Symposium, 2017

Hardware Support for Histogram-Based Performance Analysis of Embedded Systems.
Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017

A Near Optimal Integrated Solution for Resource Constrained Scheduling, Binding and Routing on CGRAs.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

ReEP: A Toolset for Generation and Programming of Reconfigurable Datapaths for Event Processing.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
RAW 2014: Random Number Generators on FPGAs.
TRETS, 2016

Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs.
Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis, 2016

RapidSoC: short turnaround creation of FPGA based SoCs.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

Optimal processor interface for CGRA-based accelerators implemented on FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Scheduler for Inhomogeneous and Irregular CGRAs with Support for Complex Control Flow.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A readback based general debugging framework for soft-core processors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs.
CoRR, 2015

Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation.
Proceedings of the 15th International Workshop on Worst-Case Execution Time Analysis, 2015

Feasibility of high level compiler optimizations in online synthesis.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014
LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Foreground detection in video streams in an FPGA without external memory.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
Runtime verification for multicore SoC with high-quality trace data.
ACM Trans. Design Autom. Electr. Syst., 2013

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Polymorphic Computers - Virtualization of Instruction Set and Microarchitecture.
Proceedings of the Informatik 2013, 2013

Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Influence of operating conditions on ring oscillator-based entropy sources in FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Towards GCC-based automatic soft-core customization.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Exploring Online Synthesis for CGRAs with Specialized Operator Sets.
Int. J. Reconfig. Comp., 2011

2010
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.
Signal Processing Systems, 2010

Low-Complexity Online Synthesis for AMIDAR Processors.
Int. J. Reconfig. Comp., 2010

A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Effects of Simplistic Online Synthesis for AMIDAR Processors.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Challenges of Electronic CAD in the Nano Scale Era.
Proceedings of the Informatik 2009: Im Focus das Leben, 2009

2008
Towards Dynamic Software/Hardware Transformation in AMIDAR Processors (Auf dem Weg zur dynamischen Software/Hardware Transformation in AMIDAR Prozessoren).
it - Information Technology, 2008

Rekonfigurierbare Architekturen.
Informatik Spektrum, 2008

Infrastructure for web-based administration of embedded systems.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

A New Methodology for the Test of SoCs and for Analyzing Elusive Failures.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Dynamic Web-Page Generation in Resource-Constrained Environments - The Kertasarie Server Pages.
Proceedings of the Third International Conference on Internet and Web Applications and Services, 2008

Acquiring an exhaustive, continuous and real-time trace from SoCs.
Proceedings of the 26th International Conference on Computer Design, 2008

A new methodology for debugging and validation of soft cores.
Proceedings of the FPL 2008, 2008

2007
A resource optimized SoC Kit for FPGAs.
Proceedings of the FPL 2007, 2007

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

A resource optimized Processor Core for FPGA based SoCs.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Predicting Hardware Acceleration Through Object Caching in AMIDAR Processors.
Proceedings of the ARCS 2006, 2006

2005
The AMIDAR Class of Reconfigurable Processors.
The Journal of Supercomputing, 2005

Hardware Based Online Profiling in AMIDAR Processors.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices.
Proceedings of the 38th Hawaii International Conference on System Sciences (HICSS-38 2005), 2005

The Organic Features of the AMIDAR Class of Processors.
Proceedings of the Systems Aspects in Organic and Pervasive Computing, 2005

2004
Distinguished Paper: A New General Model for Adaptive Processors.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003
A Datagram Based Middleware for Embedded Systems.
Proceedings of the Kommunikation in Verteilten Systemen (KiVS), 2003

2002
Ubiquitous Access to Wide-Area High-Performance Computing.
Proceedings of the Trends in Network and Pervasive Computing, 2002

2001
Prediction of Communication Performance for Wide Area Computing Systems.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

Deployment of Middleware in Resource Constrained Embedded Systems.
GI Jahrestagung (1), 2001

2000
The Cellular Processor Architecture CEPRA-1X and Its Configuration by CDL.
Proceedings of the Parallel and Distributed Processing, 2000

1999
CDL++ for the Description of Moving Objects in Cellular Automata.
Proceedings of the Parallel Computing Technologies, 1999

Remote-Administration von eingebetteten Systemen mit einem Java-basierten Add-On-Modell.
Java-Informations-Tage, 1999

1998
CDL: eine Sprache für die Zellularverarbeitung auf verschiedenen Zielplattformen.
PhD thesis, 1998

The parallel program development environment CDL/ACL for cellular processing.
Journal of Systems Architecture, 1998

1996
Automatic Generation of two Phased Models with CDL.
Proceedings of the Parcella 1996, 1996

Solving Routing Problems with Cellular Automata.
Proceedings of the ACRI '96, 1996

Hardware Supported Simulation Systems for Graph Based and 3-D Cellular Processing.
Proceedings of the ACRI '96, 1996

1995
Compilation of CDL for Different Target Architectures.
Proceedings of the Parallel Computing Technologies, 1995


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