João M. P. Cardoso

AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications.

[BibT_eX]

[DOI]

Fast Heuristic-Based GPU Compiler Sequence Specialization.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2018: Parallel Processing Workshops, 2018

ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing.

[BibT_eX]

[DOI]

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Autotuning and adaptivity in energy efficient HPC systems: the ANTAREX toolbox.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Rapid Prototyping and Verification of Hardware Modules Generated Using HLS.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

Foreword to the Special Section on Reconfigurable Computing.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

The First 25 Years of the FPL Conference: Significant Papers.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

ACM Trans. Reconfigurable Technol. Syst., 2017

Introduction to the Special Section on FPL 2015.

[BibT_eX]

[DOI]

Cristina Silvano

ACM Trans. Reconfigurable Technol. Syst., 2017

A MATLAB subset to C compiler targeting embedded systems.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2017

Introduction to the special issue on architecture of computing systems.

[BibT_eX]

[DOI]

Frank Hannig

Dietmar Fey

J. Syst. Archit., 2017

Special issue on design of algorithms and architectures for signal and image processing.

[BibT_eX]

[DOI]

Marek Gorgon

Diana Göhringer

Leandro Soares Indrusiak

J. Syst. Archit., 2017

Recent advances in computational science and engineering research.

[BibT_eX]

[DOI]

Luís Veiga

Didier El Baz

J. Comput. Sci., 2017

Foreword to the special issue of the 18th IEEE international conference on computational science and engineering (CSE2015).

[BibT_eX]

[DOI]

Christian Plessl

Guojing Cong

Concurr. Comput. Pract. Exp., 2017

The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

LARA as a language-independent aspect-oriented programming approach.

[BibT_eX]

[DOI]

Proceedings of the Symposium on Applied Computing, 2017

On Coding Techniques for Targeting FPGAs via OpenCL.

[BibT_eX]

[DOI]

Nuno Paulino

Proceedings of the Parallel Computing is Everywhere, 2017

Compiler Techniques for Efficient MATLAB to OpenCL Code Generation.

[BibT_eX]

[DOI]

Proceedings of the 5th International Workshop on OpenCL, 2017

Impact of Compiler Phase Ordering When Targeting GPUs.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

Toward a Token-Based Approach to Concern Detection in MATLAB Sources.

[BibT_eX]

[DOI]

Proceedings of the Progress in Artificial Intelligence, 2017

Expressing and Applying C++ Code Transformations for the HDF5 API Through a DSL.

[BibT_eX]

[DOI]

Proceedings of the Computer Information Systems and Industrial Management, 2017

2016

Clustering-Based Selection for the Exploration of Compiler Optimization Sequences.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach.

[BibT_eX]

[DOI]

Fernando M. Gonçalves

Softw. Pract. Exp., 2016

Pipelining data-dependent tasks in FPGA-based multicore architectures.

[BibT_eX]

[DOI]

Ali Azarian

Microprocess. Microsystems, 2016

SSA-based MATLAB-to-C compilation and optimization.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM SIGPLAN International Workshop on Libraries, 2016

A graph-based iterative compiler pass selection and phase ordering approach.

[BibT_eX]

[DOI]

José Arnaldo Mascagni de Holanda

Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

Towards a multi-softcore FPGA approach for the HOG algorithm.

[BibT_eX]

[DOI]

João Manuel Paiva Cardoso

José Arnaldo Mascagni de Holanda

Proceedings of the 14th IEEE International Conference on Industrial Informatics, 2016

Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.

[BibT_eX]

[DOI]

Cristina Silvano

Giovanni Agosta

Andrea Bartolini

Andrea Rosario Beccari

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A pipelined multi-softcore approach for the HOG algorithm.

[BibT_eX]

[DOI]

João Manuel Paiva Cardoso

Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems.

[BibT_eX]

[DOI]

Andrea Rosario Beccari

Radim Cmar

Erven Rohou

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the FPGAs for Software Programmers, 2016

2015

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Guest Editorial ARC 2014.

[BibT_eX]

[DOI]

Diana Goehringer

Marco D. Santambrogio

Koen Bertels

ACM Trans. Reconfigurable Technol. Syst., 2015

Guest Editorial FPL 2013.

[BibT_eX]

[DOI]

Katherine (Compton) Morrow

ACM Trans. Reconfigurable Technol. Syst., 2015

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2015

Fault Detection in C Programs using Monitoring of Range Values: Preliminary Results.

[BibT_eX]

[DOI]

Pedro Pinto

Rui Abreu

CoRR, 2015

Use of Previously Acquired Positioning of Optimizations for Phase Ordering Exploration.

[BibT_eX]

[DOI]

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Programming Strategies for Contextual Runtime Specialization.

[BibT_eX]

[DOI]

Pedro Pinto

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

C and OpenCL generation from MATLAB.

[BibT_eX]

[DOI]

Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Techniques for efficient MATLAB-to-C compilation.

[BibT_eX]

[DOI]

Proceedings of the 2nd ACM SIGPLAN International Workshop on Libraries, 2015

Reducing misses to external memory accesses in task-level pipelining.

[BibT_eX]

[DOI]

Ali Azarian

Cristiano Bacelar de Oliveira

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Significant papers from the first 25 years of the FPL conference.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A special-purpose language for implementing pipelined FPGA-based accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2015 Forum on Specification and Design Languages, 2015

Transparent acceleration of program execution using reconfigurable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014

A DSL for specifying run-time adaptations for embedded systems: an application to vehicle stereo navigation.

[BibT_eX]

[DOI]

J. Supercomput., 2014

Practical Education Fostered by Research Projects in an Embedded Systems Course.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2014

Specifying Dynamic Adaptations for Embedded Applications Using a DSL.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2014

Representation of Evolutionary Algorithms in FPGA Cluster for Project of Large-Scale Networks.

[BibT_eX]

[DOI]

André Bannwart Perina

Marcilyanne Moreira Gois

Paulo Matias

CoRR, 2014

Multi-Target C Code Generation from MATLAB.

[BibT_eX]

[DOI]

Proceedings of the ARRAY'14: Proceedings of the 2014 ACM SIGPLAN International Workshop on Libraries, 2014

Exploration of compiler optimization sequences using clustering-based selection.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support.

[BibT_eX]

[DOI]

João Manuel Paiva Cardoso

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

High-Level Synthesis from C vs. a DSL-Based Approach.

[BibT_eX]

[DOI]

Cristiano Bacelar de Oliveira

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

On Expressing Strategies for Directive-Driven Multicore Programing Models.

[BibT_eX]

[DOI]

Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

Coarse/Fine-grained Approaches for Pipelining Computing Stages in FPGA-Based Multicore Architectures.

[BibT_eX]

[DOI]

Ali Azarian

Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

A clustering-based approach for exploring sequences of compiler optimizations.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2014

2013

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2013

Controlling a complete hardware synthesis toolchain with LARA aspects.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Enriching MATLAB with aspect-oriented features for developing embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2013

Specifying Adaptations through a DSL with an Application to Mobile Robot Navigation.

[BibT_eX]

[DOI]

Proceedings of the 2nd Symposium on Languages, Applications and Technologies, 2013

An FPGA-based multi-core approach for pipelining computing stages.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013

The MATISSE MATLAB compiler.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Industrial Informatics, 2013

An automatic tool flow for the combined implementation of multi-mode circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Architecture for Transparent Binary Acceleration of Loops with Memory Accesses.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

LALP: A Language to Program Custom FPGA-Based Acceleration Engines.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2012

Hardware pipelining of runtime-detected loops.

[BibT_eX]

[DOI]

José Monteiro

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Hardware/software specialization through aspects: The LARA approach.

[BibT_eX]

[DOI]

Fernando M. Gonçalves

Zlatko Petrov

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Programming strategies for runtime adaptability.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Program and Aspect Metrics for MATLAB.

[BibT_eX]

[DOI]

Proceedings of the Computational Science and Its Applications - ICCSA 2012, 2012

Specifying Compiler Strategies for FPGA-based Systems.

[BibT_eX]

[DOI]

Wayne Luk

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Controlling Hardware Synthesis with Aspects.

[BibT_eX]

[DOI]

Zlatko Petrov

Wayne Luk

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Resource-Efficient Designs Using an Aspect-Oriented Approach.

[BibT_eX]

[DOI]

Sujit Bhattacharya

Wayne Luk

George A. Constantinides

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Experiments with the LARA aspect-oriented approach.

[BibT_eX]

[DOI]

Proceedings of the Companion Volume of the 11th International Conference on Aspect-oriented Software Development, 2012

LARA: an aspect-oriented programming language for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Aspect-oriented Software Development, 2012

Analysis of error detection schemes: Toolchain support and hardware/software implications.

[BibT_eX]

[DOI]

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011

Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks.

[BibT_eX]

[DOI]

Julio C. Goldner Vendramini

Alex Damiany

Tiago Teixeira

J. Syst. Archit., 2011

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010).

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2011

Identifying Merge-Beneficial Software Kernels for Hardware Implementation.

[BibT_eX]

[DOI]

Adriano K. Sanches

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

From Instruction Traces to Specialized Reconfigurable Arrays.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Techniques for Dynamically Mapping Computations to Coprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A Domain-Specific Language for the Specification of Adaptable Context Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

2010

Preprocessing techniques for context recognition from accelerometer data.

[BibT_eX]

[DOI]

Pers. Ubiquitous Comput., 2010

Providing user context for mobile and social networking applications.

[BibT_eX]

[DOI]

Pervasive Mob. Comput., 2010

The Feasibility of Navigation Algorithms on Smartphones using J2ME.

[BibT_eX]

[DOI]

André C. Santos

Luís Tarrataca

Mob. Networks Appl., 2010

Compiling for reconfigurable computing: A survey.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2010

A Query Processing Strategy for Conceptual Queries Based on Object-Role Modeling.

[BibT_eX]

[DOI]

António Rosado

Proceedings of the Fourth International Conference on Network and System Security, 2010

Welcome message.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

On identifying and optimizing instruction sequences for dynamic compilation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates.

[BibT_eX]

[DOI]

Adriano K. Sanches

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

On Identifying Segments of Traces for Dynamic Compilation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009

LALP: A Novel Language to Program Custom FPGA-Based Architectures.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

The current feasibility of gesture recognition for a smartphone using J2ME.

[BibT_eX]

[DOI]

Luís Tarrataca

André C. Santos

Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), 2009

Mobile Context Provider for Social Networking.

[BibT_eX]

[DOI]

Proceedings of the On the Move to Meaningful Internet Systems: OTM 2009 Workshops, 2009

Context Inference for Mobile Applications in the UPCASE Project.

[BibT_eX]

[DOI]

Proceedings of the Mobile Wireless Middleware, 2009

An Analysis of Navigation Algorithms for Smartphones Using J2ME.

[BibT_eX]

[DOI]

André C. Santos

Luís Tarrataca

Proceedings of the Mobile Wireless Middleware, 2009

Unbalanced FIFO sorting for FPGA-based systems.

[BibT_eX]

[DOI]

Rui Marcelino

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Code Transformations for Embedded Reconfigurable Computing Architectures.

[BibT_eX]

[DOI]

Proceedings of the Generative and Transformational Techniques in Software Engineering III, 2009

Automatic generation of FPGA hardware accelerators using a domain specific language.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks.

[BibT_eX]

[DOI]

Julio C. Goldner Vendramini

Alex Damiany

Tiago Teixeira

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

Regular Expression Matching in Reconfigurable Hardware.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2008

Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Sorting Units for FPGA-Based Embedded Systems.

[BibT_eX]

[DOI]

Rui Marcelino

Proceedings of the Distributed Embedded Systems: Design, 2008

Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007

On Pipelining Sequences of Data-Dependent Loops.

[BibT_eX]

[DOI]

Rui M. M. Rodrigues

J. Univers. Comput. Sci., 2007

On Adapting Power Estimation Models for Embedded Soft-Core Processors.

[BibT_eX]

[DOI]

José A. M. de Holanda

Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics.

[BibT_eX]

[DOI]

Rafael Peron

Denis F. Wolf

José A. M. de Holanda

Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements.

[BibT_eX]

[DOI]

Carlos Morra

Jürgen Becker

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Aggressive Loop Pipelining for Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops.

[BibT_eX]

[DOI]

Rui Rodrigues

João Miguel Gago Pontes de Brito Lima

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

A Methodology to Design FPGA-based PID Controllers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, 2006

Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures.

[BibT_eX]

[DOI]

Marcos Vinícius da Silva

Alisson Garcia

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

An Innovative Maintenance Solution for Complex Machinery: The Kobas Project Case.

[BibT_eX]

[DOI]

Proceedings of the Information Technology For Balanced Manufacturing Systems, 2006

Regular expression matching for reconfigurable packet inspection.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

New challenges in computer science education.

[BibT_eX]

[DOI]

Proceedings of the 10th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2005

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs.

[BibT_eX]

[DOI]

Rui Rodrigues

Proceedings of the 2005 Design, 2005

Dynamic loop pipelining in data-driven architectures.

[BibT_eX]

[DOI]

Proceedings of the Second Conference on Computing Frontiers, 2005

On Estimations for Compiling Software to FPGA-based Systems.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Modeling Loop Unrolling: Approaches and Open Issues.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Self-loop Pipelining and Reconfigurable Dataflow Arrays.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

A Real Time Gesture Recognition System for Mobile Robots.

[BibT_eX]

Adriano K. Sanches

Eduardo do Valle Simões

Proceedings of the ICINCO 2004, 2004

An Environment for Exploring Data-Driven Architectures.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

2003

On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Compilation for FPGA-Based Reconfigurable Hardware.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

ARCHITECT-R: A System for Reconfigurable Robots Design.

[BibT_eX]

[DOI]

Roseli A. Francelin Romero

Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms.

[BibT_eX]

[DOI]

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

From C Programs to the Configure-Execute Model.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

Fast and Guaranteed C Compilation onto the PACT-XPP? Reconfigurable Computing Platform.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2001

Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

1999

Architectures and compilers to support reconfigurable computing.

[BibT_eX]

[DOI]

Mário P. Vestístias

XRDS, 1999

An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998

Towards an automatic path from Java<sup>TM</sup> bytecodes to hardware through high-level synthesis.

[BibT_eX]

[DOI]