Martijn F. Snoeij

According to our database1, Martijn F. Snoeij authored at least 17 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A 36V 48MHz JFET-Input Bipolar Operational Amplifier with 150µV Maximum Offset and Overload Supply Current Control.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2016
Integrated Fluxgate Magnetometer for Use in Isolated Current Sensing.
IEEE J. Solid State Circuits, 2016

2015
An integrated fluxgate magnetometer for use in closed-loop/open-loop isolated current sensing.
Proceedings of the ESSCIRC Conference 2015, 2015

2011
A 36V JFET-input bipolar operational amplifier with 1μV/°C maximum offset drift and -126dB total harmonic distortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 36V voltage-to-current converter with dynamic element matching and auto-calibration for AC ripple reduction.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2009
A 36 V Programmable Instrumentation Amplifier With Sub-20µV Offset and a CMRR in Excess of 120 dB at All Gain Settings.
IEEE J. Solid State Circuits, 2009

2008
A CMOS Image Sensor with a Buried-Channel Source Follower.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 36V precision programmable gain amplifier with CMRR exceeding 120dB in all gains.
Proceedings of the ESSCIRC 2008, 2008

2007
Low-Frequency Noise Phenomena in Switched MOSFETs.
IEEE J. Solid State Circuits, 2007

Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors.
IEEE J. Solid State Circuits, 2007

A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A CMOS Imager With Column-Level ADC Using Dynamic Column Fixed-Pattern Noise Reduction.
IEEE J. Solid State Circuits, 2006

A CMOS Temperature-to-Frequency Converter With an Inaccuracy of Less Than$\pm \hbox{0.5}\, ^{\circ}{\hbox{C}}$(3$\sigma$) From$-\hbox{40}\, ^{\circ}\hbox{C}$to 105$\, ^{\circ}\hbox{C}$.
IEEE J. Solid State Circuits, 2006

A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A CMOS Temperature-to-Frequency Converter with an Inaccuracy of 0.5°C (3 σ) from -40 to 105°C.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 1.8 V 3.2µW comparator for use in a CMOS imager column-level single-slope ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2001
A 4th-order switched-capacitor sigma-delta A/D converter using a high-ripple Chebyshev loop filter.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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