Masao Sato

According to our database1, Masao Sato authored at least 10 papers between 1987 and 1997.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

1997
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems.
J. Circuits Syst. Comput., 1997

A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
A Simultaneous Placement and Global Routing Algorithm for FPGAs.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1992
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Routability of a Rubber-Band Sketch.
Proceedings of the 28th Design Automation Conference, 1991

1990
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1987
Applications of computational geometry to VLSI layout pattern design.
Integr., 1987

A Dynamic and Efficient Representation of Building-Block Layout.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987


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