Tatsuo Ohtsuki

According to our database, Tatsuo Ohtsuki authored at least 75 papers between 1976 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE Trans. Very Large Scale Integr. Syst., 2012

2011

A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit.

Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems.

Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

IPSJ Trans. Syst. LSI Des. Methodol., 2011

A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures.

Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Scan Vulnerability in Elliptic Curve Cryptosystems.

Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IPSJ Trans. Syst. LSI Des. Methodol., 2011

2010

Improved Launch for Higher TDF Coverage With Fewer Test Patterns.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures.

Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation.

Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

State-dependent changeable scan architecture against scan-based side channel attacks.

Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Scan-based attack against elliptic curve cryptosystems.

Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit.

Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding.

Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers.

Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

A Two-Level Cache Design Space Exploration System for Embedded Applications.

Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An L1 Cache Design Space Exploration System for Embedded Applications.

Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in <i>GF</i>(<i>P</i>) and <i>GF</i>(2^<i>n</i>).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures.

Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Scan-Based Attack Based on Discriminators for AES Cryptosystems.

Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Design-for-secure-test for crypto cores.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2009 IEEE International Test Conference, 2009

Exact and fast L1 cache simulation for embedded systems.

Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures.

Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IPSJ Trans. Syst. LSI Des. Methodol., 2008

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Secure Test Technique for Pipelined Advanced Encryption Standard.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Inf. Syst., 2008

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2ⁿ).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

GECOM: Test data compression combined with all unknown response masking.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm.

Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Unknown response masking with minimized observable response loss and mask data.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding.

Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier.

Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Electron., 2006

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains.

Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.

Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.

Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Inf. Syst., 2005

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis.

Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.

Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low Power Test Compression Technique for Designs with Multiple Scan Chain.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A processor core synthesis system in IP-based SoC design.

Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.

Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A thread partitioning algorithm in low power high-level synthesis.

Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Instruction set and functional unit synthesis for SIMD processor cores.

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths.

Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories.

Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions.

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions.

Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation.

Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A hardware/software partitioning algorithm for SIMD processor cores.

Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation.

Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks.

Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation.

Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

VLSI Architecture for a Flexible Motion Estimation with Parameters.

Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.

Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Area/delay estimation for digital signal processor cores.

Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of ASP-DAC 2001, 2001

2000

An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper).

Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of ASP-DAC 2000, 2000

1999

Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations.

Tingrong Zhao, Masao Yanagisawa, Tatsuo Ohtsuki

J. Circuits Syst. Comput., 1999

A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization.

Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki

J. Circuits Syst. Comput., 1999

A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing.

Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.

Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the ASP-DAC '98, 1998

A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs.

Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the ASP-DAC '98, 1998

1997

A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems.

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

J. Circuits Syst. Comput., 1997

A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs.

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995

Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization.

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

A Simultaneous Placement and Global Routing Algorithm for FPGAs.

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1992

An optimal chip compaction method based on shortest path algorithm with automatic jog insertion.

Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1990

Recent advances in VLSI layout.

Ernest S. Kuh, Tatsuo Ohtsuki

Proc. IEEE, 1990

A Hardware Implementation of Gridless Routing Based on Content Addressable Memory.

Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1987

Applications of computational geometry to VLSI layout pattern design.

Masao Sato, Tatsuo Ohtsuki

Integr., 1987

1986

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute.

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

1981

On Minimal Augmentation of a Graph to Obtain an Interval Graph.

Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa

J. Comput. Syst. Sci., 1981

1980

The two disjoint path problem and wire routing design.

Tatsuo Ohtsuki

Proceedings of the Graph Theory and Algorithms, 1980

1979

One-dimensional logic gate assignment and interval graphs.

Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa

Proceedings of the IEEE Computer Society's Third International Computer Software and Applications Conference, 1979

1976

A Fast Algorithm for Finding an Optimal Ordering for Vertex Elimination on a Graph.

Tatsuo Ohtsuki

SIAM J. Comput., 1976