Masaru Osada

According to our database, Masaru Osada authored at least 6 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.

Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation.

Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.

Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering.

Masaru Osada, Zule Xu, Tetsuya Iizuka

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021

A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur.

Zule Xu, Masaru Osada, Tetsuya Iizuka

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur.

Masaru Osada, Zule Xu, Tetsuya Iizuka

Proceedings of the IEEE Symposium on VLSI Circuits, 2020