Zule Xu
Orcid: 0000-0001-6899-3860
According to our database1,
Zule Xu
authored at least 30 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
23.5 A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEICE Trans. Electron., October, 2023
2022
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration.
IEEE J. Solid State Circuits, 2022
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving -232.8-dB FoMref.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.
IEICE Trans. Electron., 2019
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool.
IEICE Electron. Express, 2019
A 0.0053-mm<sup>2</sup> 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2017
A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design.
IEICE Trans. Electron., 2017
Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs.
IEICE Trans. Electron., 2017
Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error.
IEICE Trans. Electron., 2017
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator.
IEICE Trans. Electron., 2017
2016
IEEE J. Solid State Circuits, 2016
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
2011
IEICE Trans. Electron., 2011