Zunsong Yang

According to our database, Zunsong Yang authored at least 11 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

7.4 A 0.027mm² 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.

Yunbo Huang, Yong Chen, Zunsong Yang, Rui Paulo Martins, Pui-In Mak

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.

Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit.

Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka

Proceedings of the International Conference on IC Design and Technology, 2023

Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit.

Zhenyu Cheng, Zunsong Yang, Yuyang Zhu, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka

Proceedings of the International Conference on IC Design and Technology, 2023

2022

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.

Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Very Large Scale Integr. Syst., 2022

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.

Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A 0.003-mm² 440fs_RMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.

Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.

Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins

IEEE Access, 2020

2019

A 0.0071-mm² 10.8ps_pp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.

Yong Chen, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.

Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.003-mm² 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.

Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019