Zunsong Yang
Orcid: 0000-0001-8539-8481
According to our database1,
Zunsong Yang authored at least 24 papers
between 2019 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
A 22.4-25.6-GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction.
IEEE J. Solid State Circuits, June, 2026
A 5.4-GHz reference-sampling PLL-sub-sampling DLL cascaded frequency synthesizer achieving 85.7-fs RMS jitter in 65-nm CMOS.
Microelectron. J., 2026
Microelectron. J., 2026
25.10 A 65nm 0.066pJ/b Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 2-GHz 5.06-mW Phase Accumulator Employing Dynamic Regulation for High-Speed Direct Digital Frequency Synthesizers in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A D-Band Power Amplifier with A Novel Gain-Boosting Structure Achieving 15.8-dB Gain and 23.9-GHz Bandwidth in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC.
Circuits Syst. Signal Process., May, 2025
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment.
IEEE J. Solid State Circuits, March, 2025
A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2<sup>nd</sup> Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering.
IEEE J. Solid State Circuits, July, 2024
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
7.4 A 0.027mm<sup>2</sup> 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit.
Proceedings of the International Conference on IC Design and Technology, 2023
Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit.
Proceedings of the International Conference on IC Design and Technology, 2023
2022
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A 0.003-mm<sup>2</sup> 440fs<sub>RMS</sub>-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.
IEEE Access, 2020
2019
A 0.0071-mm<sup>2</sup> 10.8ps<sub>pp</sub>-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.003-mm<sup>2</sup> 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019