Masayoshi Sakao

According to our database, Masayoshi Sakao authored at least 3 papers between 1993 and 1994.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1994

A high-density data-path generator with stretchable cells.

Yoshiki Tsujihashi, Hisashi Matsumoto, Hidekatsu Nishimaki, Atsushi Miyanishi, Hiroomi Nakao, Osamu Kitada, Shuhei Iwade, Shinpei Kayano, Masayoshi Sakao

IEEE J. Solid State Circuits, January, 1994

1993

A 1.71-million transistor CMOS CPU chip with a testable cache architecture.

Yuichi Saito, Yukihiko Shimazu, Tom Shimizu, Kenji Shirai, Isao Fujioka, Yoshitetsu Nishiwaki, Junichi Hinata, Yoshiki Shimotsuma, Masayoshi Sakao

IEEE J. Solid State Circuits, November, 1993

A VLSI chip set for a large-scale parallel inference machine: PIM/m.

Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao, Masao Nakaya

IEEE J. Solid State Circuits, March, 1993