Yukihiko Shimazu

According to our database, Yukihiko Shimazu authored at least 7 papers between 1986 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu

IEEE J. Solid State Circuits, 2007

2006

A 40GOPS 250mW massively parallel processor based on matrix architecture.

Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1996

Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor.

Mamoru Sakamoto, Toyohiko Yoshida, Yasuhiro Nunomura, Yukihiko Shimazu

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1993

A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.

Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1990

Built-in self-test in a 24 bit floating point digital signal processor.

Narumi Sakashita, Hisako Sawai, Eiichi Teraoka, Toshiki Fugiyama, Toru Kengaku, Yukihiko Shimazu, Takeshi Tokuda

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988

A macrocell approach for VLSI processor design.

Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1986

A next-generation 32-bit VLSI signal processor.

Shingo Tsujimichi, TakaHide Ohkami, Yukihiko Shimazu

Proceedings of the IEEE International Conference on Acoustics, 1986