Hideki Ando

According to our database1, Hideki Ando authored at least 30 papers between 1993 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison.
IEICE Trans. Inf. Syst., 2022

Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2019
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline.
IEEE Comput. Archit. Lett., 2019

SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications.
J. Inf. Process., 2018

Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Rearranging Random Issue Queue with High IPC and Short Delay.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2016
FXA: Executing Instructions in Front-End for Energy Efficiency.
IEICE Trans. Inf. Syst., 2016

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency.
IEICE Trans. Inf. Syst., 2016

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control.
IEICE Trans. Inf. Syst., 2016

2014
MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism.
IEICE Trans. Inf. Syst., 2014

A Front-End Execution Architecture for High Energy Efficiency.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Energy efficiency improvement of renamed trace cache through the reduction of dependent path length.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification.
IEICE Trans. Inf. Syst., 2012

2011
Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction.
IEICE Trans. Inf. Syst., 2010

2009
Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation.
IEICE Trans. Inf. Syst., 2009

Reducing register file size through instruction pre-execution enhanced by value prediction.
Proceedings of the 27th International Conference on Computer Design, 2009

2007
Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation.
Proceedings of the 2007 workshop on MEmory performance, 2007

2003
Pipeline stage unification: a low-energy consumption technique for future mobile processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
A preactivating mechanism for a VT-CMOS cache using address prediction.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1999
Distributed memoryless point convergence algorithm for mobile robots with limited visibility.
IEEE Trans. Robotics Autom., 1999

An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
Software pipelining with path selection.
Syst. Comput. Jpn., 1998

1996
Performance Comparison of ILP Machines with Cycle Time Evaluation.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

1995
Code scheduling on a superscalar processor: SARCH.
Syst. Comput. Jpn., 1995

Unconstrained Speculative Execution with Predicated State Buffering.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1993
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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