Hiroshi Nakashima

  • Academic Center for Computing and Media Studies, Kyoto University

According to our database1, Hiroshi Nakashima authored at least 59 papers between 1984 and 2022.

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In proceedings 
PhD thesis 


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On csauthors.net:


Energy Aware Scheduler of Single/Multi-Node Jobs Considering CPU Node Heterogeneity.
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022

Accelerating the SpMV kernel on standard CPUs by exploiting the partially diagonal structures.
CoRR, 2021

Core body temperature estimation by eyeglass-type device: thermal analysis of radiation heat measured from caruncle.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

QR Factorization of Block Low-rank Matrices with Weak Admissibility Condition.
J. Inf. Process., 2019

Parallelization of Matrix Partitioning in Construction of Hierarchical Matrices using Task Parallel Languages.
J. Inf. Process., 2019

Enhancing support for optimal muscle usage in sports: coaching and skill-improvement tracking with sEMG.
Proceedings of the 23rd International Symposium on Wearable Computers, ISWC 2019, London, 2019

SiN used as a Stressor in Germanium-On-Insulator Substrate.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Parallel Hierarchical Matrices with Block Low-rank Representation on Distributed Memory Computer Systems.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2018

Parallelization of Extracting Connected Subgraphs with Common Itemsets in Distributed Memory Environments.
J. Inf. Process., 2017

Large Scale Manycore-Aware PIC Simulation with Efficient Particle Binning.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Reducing Redundant Search in Parallel Graph Mining Using Exceptions.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Manycore challenge in particle-in-cell simulation: How to exploit 1 TFlops peak performance for simulation codes with irregular computation.
Comput. Electr. Eng., 2015

A New Fill-in Strategy for IC Factorization Preconditioning Considering SIMD Instructions.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Automatic Parameter Tuning of Three-Dimensional Tiled FDTD Kernel.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2014 - 11th International Conference, Eugene, OR, USA, June 30, 2014

SIMD Implementation of a Multiplicative Schwarz Smoother for a Multigrid Poisson Solver on an Intel Xeon Phi Coprocessor.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2014 - 11th International Conference, Eugene, OR, USA, June 30, 2014

Low-Cost Load Balancing for Parallel Particle-in-Cell Simulations with Thick Overlapping Layers.
Proceedings of the 12th IEEE International Conference on Trust, 2013

Parallel Smoother Based on Block Red-Black Ordering for Multigrid Poisson Solver.
Proceedings of the High Performance Computing for Computational Science, 2012

Algebraic Block Multi-Color Ordering Method for Parallel Multi-Threaded Sparse Triangular Solver in ICCG Method.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Fast Computation of Quasi-Dynamic Earthquake Cycle Simulation with Hierarchical Matrices.
Proceedings of the International Conference on Computational Science, 2011

Efficient Representation of Constraints and Propagation of Variable-Value Symmetries in Distributed Constraint Reasoning.
J. Inf. Process., 2011

The International Exascale Software Project roadmap.
Int. J. High Perform. Comput. Appl., 2011

OhHelp: a scalable domain-decomposing dynamic load balancing for particle-in-cell simulations.
Proceedings of the 23rd international conference on Supercomputing, 2009

A traffic control method with channel occupancy information from MAC layer in IEEE 802.11.
Proceedings of the 2009 International Conference on Information Networking, 2009

A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions.
IPSJ Trans. Syst. LSI Des. Methodol., 2008

Saving 200kW and 200 K/year by power-aware job/machine scheduling.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Design and evaluation of an auto-memoization processor.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators.
Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007

MegaProto/E: power-aware high-performance cluster with commodity technology.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

An accurate and efficient simulation-based analysis for worst case interruption delay.
Proceedings of the 2006 International Conference on Compilers, 2006

Design and Implementation of aWorkload Specific Simulator.
Proceedings of the Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2006

MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology.
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

An Efficient Search Algorithm of Worst-Case Cache Flush Timings.
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Parallel Program Debugging based on Data-Replay.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

MegaProto: A Low-Power and Compact Cluster for High-Performance Computing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Design and Implementation of a High Speed Microprocessor Simulator BurstScalar.
Proceedings of the 12th International Workshop on Modeling, 2004

Shaman: A Distributed Simulator for Shared Memory Multiprocessors.
Proceedings of the 10th International Workshop on Modeling, 2002

Reference Filtering for Distributed Simulation of Shared Memory Multiprocessors.
Proceedings of the Proceedings 34th Annual Simulation Symposium (SS 2001), 2001

Satellite communication system integrated into terrestrial ISDN.
IEEE Trans. Aerosp. Electron. Syst., 2000

Orgel: A Parallel Programming Language with Declarative Communication Streams.
Proceedings of the High Performance Computing, Third International Symposium, 2000

A Mechanism for Speculative Memory Accesses Following Synchronizing Operations.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.
Int. J. Parallel Program., 1999

Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

Exploiting Parallel Computers to Reduce Neural Network Training Time of Real Applications.
Proceedings of the High Performance Computing, International Symposium, 1997

Improvement of message communication in concurrent logic language.
Proceedings of the 2nd International Workshop on Parallel Symbolic Computation, 1997

Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis.
Proceedings of the Advances in Computing Science, 1997

Amon2: A Parallel Wire Routing Algorithm on a Torus Network Parallel Computer.
Proceedings of the 10th international conference on Supercomputing, 1996

Amon: A Parallel Slice Algorithm for Wire Routing.
Proceedings of the 9th international conference on Supercomputing, 1995

General mapping of feed-forward neural networks onto an MIMD computer.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

A proposal of self-cleanup cache.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.
Proceedings of the International Symposium on Parallel Architectures, 1994

A New Satellite Communication System Integrated into Public Switched Networks. - DYANET.
IEEE J. Sel. Areas Commun., 1992

Architecture and Implementation of PIM/m.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992

A load balancing mechanism for large scale multiprocessor systems and its implementation.
New Gener. Comput., 1990

A pipelined microprocessor for logic programming languages.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

An Efficient Termination Detection and Abortion Algorithm for Distributed Processing Systems.
Proceedings of the International Conference on Parallel Processing, 1988

Hardware Architecture of the Sequential Inference Machine: PSI-II.
Proceedings of the 1987 Symposium on Logic Programming, San Francisco, California, USA, August 31, 1987

Performance and Architectural Evaluation of the PSI Machine.
Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), 1987

Evaluation of PSI Micro-Interpreter.
Proceedings of the Spring COMPCON'86, 1986

Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).
Proceedings of the International Conference on Fifth Generation Computer Systems, 1984