Masayuki Shimoda

Orcid: 0000-0003-4627-0957

According to our database1, Masayuki Shimoda authored at least 21 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Pre- and post-processing techniques for reinforcement-learning-based routing and spectrum assignment in elastic optical networks.
J. Opt. Commun. Netw., December, 2023

2021
FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling.
J. Signal Process. Syst., 2021

Impact of Operational Mode Selection and Grooming Policies on Auxiliary Graph-Based Multi-layer Network Planning.
Proceedings of the European Conference on Optical Communication, 2021

Mask RSA: End-To-End Reinforcement Learning-based Routing and Spectrum Assignment in Elastic Optical Networks.
Proceedings of the European Conference on Optical Communication, 2021

2020
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators.
IEICE Trans. Inf. Syst., 2020

Fast Monocular Depth Estimation on an FPGA.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2019
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA.
IEICE Trans. Inf. Syst., 2019

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers.
IEICE Trans. Inf. Syst., 2019

FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2019

An FPGA Implementation of Real-Time Object Detection with a Thermal Camera.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

An FPGA-based Fine Tuning Accelerator for a Sparse CNN.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Power Efficient Object Detector with an Event-Driven Camera on an FPGA.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2).
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
All binarized convolutional neural network and its implementation on an FPGA.
Proceedings of the International Conference on Field Programmable Technology, 2017

A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017


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