Shimpei Sato

According to our database, Shimpei Sato authored at least 50 papers between 2009 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Humanoid Walking System with CNN-Based Uneven Terrain Recognition and Landing Control with Swing-Leg Velocity Constraints.

Shimpei Sato, Kunio Kojima, Naoki Hiraoka, Kei Okada, Masayuki Inaba

IROS, 2023

Whole-Body Torque Control Without Joint Position Control Using Vibration-Suppressed Friction Compensation for Bipedal Locomotion of Gear-Driven Torque Sensorless Humanoid.

Takuma Hiraoka, Shimpei Sato, Naoki Hiraoka, Annan Tang, Kunio Kojima, Kei Okada, Masayuki Inaba, Koji Kawasaki

IROS, 2023

2022

Robust Humanoid Walking System Considering Recognized Terrain and Robots' Balance.

Shimpei Sato, Yuta Kojio, Yohei Kakiuchi, Kunio Kojima, Kei Okada, Masayuki Inaba

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

Trajectory Generation and Compensation for External Forces with a Leg-wheeled Robot Designed for Human Passengers.

Yohei Kakiuchi, Yuta Kojio, Noriaki Imaoka, Daiki Kusuyama, Shimpei Sato, Yutaro Matsuura, Takeshi Ando, Masayuki Inaba

Proceedings of the 21st IEEE-RAS International Conference on Humanoid Robots, 2022

2021

Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder.

Naoto Soga, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2021

Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs.

Akira Jinguji, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2021

Drop Prevention Control for Humanoid Robots Carrying Stacked Boxes.

Shimpei Sato, Yuta Kojio, Kunio Kojima, Fumihito Sugai, Yohei Kakiuchi, Kei Okada, Masayuki Inaba

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

2020

SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators.

Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2020

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections.

Shimpei Sato, Kano Akagi, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

A Table Look-Up Based Ternary Neural Network Processor.

Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Fast Monocular Depth Estimation on an FPGA.

Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs.

Akira Jinguji, Shimpei Sato, Hiroki Nakahara

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2019

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution.

Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers.

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato

IEICE Trans. Inf. Syst., 2019

FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System.

Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks.

Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Noise Convolutional Neural Networks and FPGA Implementation.

Atsuki Munakata, Hiroki Nakahara, Shimpei Sato

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution.

Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network.

Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

An FPGA-based Fine Tuning Accelerator for a Sparse CNN.

Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

IEEE J. Solid State Circuits, 2018

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment.

Shimpei Sato, Ryohei Kobayashi, Kenji Kise

IEICE Trans. Inf. Syst., 2018

An FPGA Realization of a Random Forest with <i>k</i>-Means Clustering Using a High-Level Synthesis Design.

Akira Jinguji, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2018

A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA.

Tomoya Fujii, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2018

Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses.

Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Power Efficient Object Detector with an Event-Driven Camera on an FPGA.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS).

Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector.

Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato

Proceedings of the International Conference on Field-Programmable Technology, 2018

An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network.

Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara

Proceedings of the International Conference on Field-Programmable Technology, 2018

Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2).

Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA.

Thiem Van Chu, Shimpei Sato, Kenji Kise

ACM Trans. Reconfigurable Technol. Syst., 2017

In-memory area-efficient signal streaming processor design for binary neural networks.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

All binarized convolutional neural network and its implementation on an FPGA.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the International Conference on Field Programmable Technology, 2017

An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA.

Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato

Proceedings of the International Conference on Field Programmable Technology, 2017

A fully connected layer elimination for a binarizec convolutional neural network on an FPGA.

Hiroki Nakahara, Tomoya Fujii, Shimpei Sato

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2015

Investigating potential performance benefits of memory layout optimization based on roofline model.

Shimpei Sato, Yukinori Sato, Toshio Endo

Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

Exana: an execution-driven application analysis tool for assisting productive performance tuning.

Yukinori Sato, Shimpei Sato, Toshio Endo

Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

Effective Parallel Simulation of ArchHDL under Manycore Environment.

Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, Kenji Kise

Proceedings of the Third International Symposium on Computing and Networking, 2015

Ultra-fast NoC emulation on a single FPGA.

Thiem Van Chu, Shimpei Sato, Kenji Kise

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA.

Thiem Van Chu, Shimpei Sato, Kenji Kise

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

ArchHDL: A Novel Hardware RTL Design Environment in C++.

Shimpei Sato, Kenji Kise

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs.

Thiem Van Chu, Shimpei Sato, Kenji Kise

Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

2013

The Ultrasmall soft processor.

Yuichiro Tanaka, Shimpei Sato, Kenji Kise

SIGARCH Comput. Archit. News, 2013

2010

Smart Core System for Dependable Many-Core Processor with Multifunction Routers.

Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise

Proceedings of the First International Conference on Networking and Computing, 2010

Pattern-Based Systematic Task Mapping for Many-Core Processors.

Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise

Proceedings of the First International Conference on Networking and Computing, 2010

2009

A Study of an Infrastructure for Research and Development of Many-Core Processors.

Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise

Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009