Maurice Jamieson

According to our database, Maurice Jamieson authored at least 13 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A shared compilation stack for distributed-memory parallelism in stencil DSLs.

George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU.

Nick Brown, Maurice Jamieson, Joseph K. L. Lee, Paul Wang

CoRR, 2023

Experiences of running an HPC RISC-V testbed.

Nick Brown, Maurice Jamieson, Joseph K. L. Lee

CoRR, 2023

Test-Driving RISC-V Vector Hardware for HPC.

Joseph K. L. Lee, Maurice Jamieson, Nick Brown, Ricardo Jesus

Proceedings of the High Performance Computing, 2023

Backporting RISC-V Vector Assembly.

Joseph K. L. Lee, Maurice Jamieson, Nick Brown

Proceedings of the High Performance Computing, 2023

Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA.

Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU.

Nick Brown, Maurice Jamieson, Joseph K. L. Lee, Paul Wang

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang.

Nick Brown, Maurice Jamieson, Anton Lydike, Emilien Bauer, Tobias Grosser

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

2022

Performance of the Vipera Framework for DSLs on Micro-Core Architectures.

Maurice Jamieson, Nick Brown

Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022

2021

Compact native code generation for dynamic languages on micro-core architectures.

Maurice Jamieson, Nick Brown

Proceedings of the CC '21: 30th ACM SIGPLAN International Conference on Compiler Construction, 2021

2020

High level programming abstractions for leveraging hierarchical memories with micro-core architectures.

Maurice Jamieson, Nick Brown

J. Parallel Distributed Comput., 2020

Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython.

Maurice Jamieson, Nick Brown, Sihang Liu

Proceedings of the 19th Python in Science Conference 2020 (SciPy 2020), Virtual Conference, July 6, 2020

Benchmarking micro-core architectures for detecting disasters at the edge.

Maurice Jamieson, Nick Brown

Proceedings of the IEEE/ACM HPC for Urgent Decision Making, UrgentHPC@SC 2020, Atlanta, GA, 2020