Mayank Palaria

According to our database, Mayank Palaria authored at least 5 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS.

Soumya Mahapatra, Mostafa M. Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, Mike Shuo-Wei Chen

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems.

Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS.

Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems.

Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan M. Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan A. Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2019

Adder-Only Convolutional Neural Network with Binary Input Image.

Mayank Palaria, Sai Sanjeet, Bibhu Datta Sahoo, Masahiro Fujita

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019