Md. Mazder Rahman

According to our database1, Md. Mazder Rahman authored at least 15 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2018
Optimization of Circuits for IBM's Five-Qubit Quantum Computers.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2016
GarCoSim: A Framework for Automated Memory Management Research and Evaluation.
EAI Endorsed Trans. Scalable Inf. Syst., 2016

Trace Files for Automatic Memory Management Systems.
Proceedings of the First International Workshop on Validating Software Tests, 2016

Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

An extension of transformation-based reversible and quantum circuit synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Synthesis of Linear Nearest Neighbor Quantum Circuits.
CoRR, 2015

Dynamic Template Matching with Mixed-Polarity Toffoli Gates.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014
An Algorithm for Quantum Template Matching.
ACM J. Emerg. Technol. Comput. Syst., 2014

2012
Properties of Quantum Templates.
Proceedings of the Reversible Computation, 4th International Workshop, 2012

Optimal Quantum Circuits of Three Qubits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

An algorithm to find quantum templates.
Proceedings of the IEEE Congress on Evolutionary Computation, 2012

2011
Optimization of Reversible Circuits Using Reconfigured Templates.
Proceedings of the Reversible Computation - Third International Workshop, 2011

Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2004
On the Minimization of Multiple-Valued Input Binary-Valued Output Functions.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004


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