Robert Wille

According to our database1, Robert Wille authored at least 323 papers between 1993 and 2020.

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Bibliography

2020
Simulation and Design of Quantum Circuits.
Proceedings of the Reversible Computation: Extending Horizons of Computing, 2020

Harnessing the Granularity of Micro-Electrode-Dot-Array Architectures for Optimizing Droplet Routing in Biochips.
ACM Trans. Design Autom. Electr. Syst., 2020

Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Overcoming the Tradeoff Between Accuracy and Compactness in Decision Diagrams for Quantum Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Improved Mapping of Quantum Circuits to IBM QX Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Automatic Droplet Sequence Generation for Microfluidic Networks With Passive Droplet Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Robustness Analysis for Droplet-Based Microfluidic Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation.
IEEE Trans. Computers, 2020

On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata.
Microprocess. Microsystems, 2020

Modeling and simulation of electrophoretic deposition coatings.
J. Comput. Sci., 2020

Near Zero-Energy Computation Using Quantum-Dot Cellular Automata.
ACM J. Emerg. Technol. Comput. Syst., 2020

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD).
Integr., 2020

Design and realization of flexible droplet-based lab-on-a-chip devices.
Elektrotech. Informationstechnik, 2020

Random Stimuli Generation for the Verification of Quantum Circuits.
CoRR, 2020

Model-driven Engineering of Safety and Security Systems: A Systematic Mapping Study.
CoRR, 2020

Advanced Equivalence Checking for Quantum Circuits.
CoRR, 2020

Post Synthesis-Optimization of Reversible Circuit using Template Matching.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Integer Overflow Detection in Hardware Designs at the Specification Level.
Proceedings of the 8th International Conference on Model-Driven Engineering and Software Development, 2020

Automatic compiler optimization on embedded software through k-means clustering.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Cost Optimization at Early Stages of Design Using Deep Reinforcement Learning.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing Circuits.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

YASSi: Yet Another Symbolic Simulator Large (Tool Demo).
Proceedings of the Database and Expert Systems Applications, 2020

Verification Runtime Analysis: Get the Most Out of Partial Verification.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Towards Exploring the Potential of Alternative Quantum Computing Architectures.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Realizing Quantum Algorithms on Real Quantum Computing Devices.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Verification for Field-coupled Nanocomputing Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Just Like the Real Thing: Fast Weak Simulation of Quantum Computation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

The Power of Simulation for Equivalence Checking in Quantum Computing.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Approximation of Quantum States Using Decision Diagrams.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Concurrency in DD-based Quantum Circuit Simulation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Improved DD-based Equivalence Checking of Quantum Circuits.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Towards Automatic Hardware Synthesis from Formal Specification to Implementation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Passive Droplet Control in Two-Dimensional Microfluidic Networks.
IEEE Trans. Mol. Biol. Multi Scale Commun., 2019

Locking the Design of Building Blocks for Quantum Circuits.
ACM Trans. Embed. Comput. Syst., 2019

Advanced Simulation of Quantum Computations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Automated Dimensioning of Networked Labs-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Passive droplet control in microfluidic networks: A survey and new perspectives on their practical realization.
Nano Commun. Networks, 2019

Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications.
Microprocess. Microsystems, 2019

Faster manipulation of large quantum circuits using wire label reference diagrams.
Microprocess. Microsystems, 2019

Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is <i>NP</i>-complete (Research Note).
ACM J. Emerg. Technol. Comput. Syst., 2019

Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2019

Advanced Simulation of Droplet Microfluidics.
ACM J. Emerg. Technol. Comput. Syst., 2019

fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits.
CoRR, 2019

Dilution with Digital Microfluidic Biochips: How Unbalanced Splits Corrupt Target-Concentration.
CoRR, 2019

Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Evaluating the Flexibility of A* for Mapping Quantum Circuits.
Proceedings of the Reversible Computation - 11th International Conference, 2019

Simulating Industrial Electrophoretic Deposition on Distributed Memory Architectures.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

Information Encoding in Droplet-Based Microfluidic Systems: First Practical Study.
Proceedings of the Sixth Annual ACM International Conference on Nanoscale Computing and Communication, 2019

Did We Test Enough? Functional Coverage for Post-Silicon Validation.
Proceedings of the IEEE International Test Conference in Asia, 2019

Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Flow-Based Passive Microfluidic Architecture for Homogeneous Mixing.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

Exact Stimuli Minimization for Simulation-Based Verification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

How to Efficiently Handle Complex Values? Implementing Decision Diagrams for Quantum Computing.
Proceedings of the International Conference on Computer-Aided Design, 2019

Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines.
Proceedings of the International Conference on Computer-Aided Design, 2019

Generic Error Localization for the Electronic System Level.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Matrix-Vector vs. Matrix-Matrix Multiplication: Potential in DD-based Simulation of Quantum Computations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accuracy and Compactness in Decision Diagrams for Quantum Computation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

IBM's Qiskit Tool Chain: Working with and Developing for Real Quantum Computers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Better Late Than Never : Verification of Embedded Systems After Deployment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Mapping Quantum Circuits to IBM QX Architectures Using the Minimal Number of SWAP and H Operations.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Compiling SU(4) quantum circuits to IBM QX architectures.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Design automation for adiabatic circuits.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A staircase structure for scalable and efficient synthesis of memristor-aided logic.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Robust sample preparation on digital microfluidic biochips.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Scalable design for field-coupled nanocomputing circuits.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Effect of Volumetric Split-Errors on Reactant-Concentration During Sample Preparation with Microfluidic Biochips.
Proceedings of the Advanced Computing and Systems for Security, 2019

2018
One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Design of Application-Specific Architectures for Networked Labs-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams.
Microelectron. J., 2018

Preface to the Special Issue of the 48th IEEE International Symposium on Multiple Valued Logic.
FLAP, 2018

Breaking Landauer's Limit\\Using Quantum-dot Cellular Automata.
CoRR, 2018

NISQ circuit compilers: search space structure and heuristics.
CoRR, 2018

Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of <i>modifies only</i> statements.
Comput. Lang. Syst. Struct., 2018

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

QMDD-Based One-Pass Design of Reversible Logic: Exploring the Available Degree of Freedom (Work-in-Progress Report).
Proceedings of the Reversible Computation - 10th International Conference, 2018

Comparison of switching principles in microfluidic bus networks.
Proceedings of the 5th ACM International Conference on Nanoscale Computing and Communication, 2018

Generation and Validation of Frame Conditions in Formal Models.
Proceedings of the Model-Driven Engineering and Software Development, 2018

Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence.
Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development, 2018

A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-Valued Logic.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Synthesis of Reversible Circuits Using Conventional Hardware Description Languages.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Parallel Simulation of Electrophoretic Deposition for Industrial Automotive Applications.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning.
Proceedings of the 8th International Workshop on Combinations of Intelligent Methods and Applications co-located with 30th International Conference on Artificial Intelligence Tools (ICTAI 2018), 2018

Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips.
Proceedings of the International Conference on Computer-Aided Design, 2018

Computer-aided design for quantum computation.
Proceedings of the International Conference on Computer-Aided Design, 2018

IC/IP piracy assessment of reversible logic.
Proceedings of the International Conference on Computer-Aided Design, 2018

AMulti-GPU PCISPH Implementation with Efficient Memory Transfers.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Automatic Design of Microfluidic Devices.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Pushing the number of qubits below the "minimum": Realizing compact boolean components for quantum logic.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Efficient mapping of quantum circuits to the IBM QX architectures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

An exact method for design exploration of quantum-dot cellular automata.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improved synthesis of Clifford+T quantum functionality.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Exploiting coding techniques for logic synthesis of reversible circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Sound valve-control for programmable microfluidic devices.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Emerging Circuit Technologies: An Overview on the Next Generation of Circuits.
Proceedings of the Advanced Logic Synthesis, 2018

Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers
Springer, ISBN: 978-3-319-72813-1, 2018

2017
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1).
NII Shonan Meet. Rep., 2017

Towards quantum reversible ternary coded decimal adder.
Quantum Inf. Process., 2017

Online scheduled execution of quantum circuits protected by surface codes.
Quantum Inf. Comput., 2017

An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs.
J. Low Power Electron., 2017

Synthesis of optical circuits using binary decision diagrams.
Integr., 2017

Formal methods for reasoning and uncertainty reduction in evidential grid maps.
Int. J. Approx. Reason., 2017

Advanced Simulation of Quantum Computations: Compact Representation Rather than Hardware Power.
CoRR, 2017

Towards Reverse Engineering Reversible Logic.
CoRR, 2017

On the Difficulty of Inserting Trojans in Reversible Computing Architectures.
CoRR, 2017

Design automation for Labs-on-Chip: A new "playground" for SoC designers.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Improving Synthesis of Reversible Circuits: Exploiting Redundancies in Paths and Nodes of QMDDs.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Exact Global Reordering for Nearest Neighbor Quantum Circuits Using A ^* ∗.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits - Work in Progress Report.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Test Pattern Generation Effort Evaluation of Reversible Circuits.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Exploiting reversible logic design for implementing adiabatic circuits.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Verifikation von Networked Labs-on-Chip Architekturen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Skipping Embedding in the Design of Reversible Circuits.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

OR-Inverter Graphs for the Synthesis of Optical Circuits.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Extensions to the Reversible Hardware Description Language SyReC.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Towards lightweight satisfiability solvers for self-verification.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Addressing multiple nodes in networked labs-on-chips without payload re-injection.
Proceedings of the IEEE International Conference on Communications, 2017

Advanced load balancing for SPH simulations on multi-GPU architectures.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Tagged BDDs: Combining reduction rules from different decision diagram types.
Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

Stochastic Computing Using Droplet-Based Microfluidics.
Proceedings of the Computer Aided Systems Theory - EUROCAST 2017, 2017

Formulating Model Verification Tasks Prover-Independently as UML Diagrams.
Proceedings of the Modelling Foundations and Applications - 13th European Conference, 2017

An efficient physical design of fully-testable BDD-based circuits.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Taking one-to-one mappings for granted: Advanced logic design of encoder circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Make it reversible: Efficient embedding of non-reversible functions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Verification of networked Labs-on-Chip architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design Automation.
Proceedings of the 54th Annual Design Automation Conference, 2017

Exact routing for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Enhancing robustness of sequential circuits using application-specific knowledge and formal methods.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Close-to-optimal placement and routing for continuous-flow microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
QMDDs: Efficient Quantum Function Representation and Manipulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Embedding of Large Boolean Functions for Reversible Logic.
ACM J. Emerg. Technol. Comput. Syst., 2016

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2016

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability.
ACM J. Emerg. Technol. Comput. Syst., 2016

Analyzing Inconsistencies in UML/OCL Models.
J. Circuits Syst. Comput., 2016

SyReC: A hardware description language for the specification and synthesis of reversible circuits.
Integr., 2016

Verifying the structure and behavior in UML/OCL models using satisfiability solvers.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Reliable quantum circuits have defects.
XRDS, 2016

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Extracting frame conditions from operation contracts.
Proceedings of the Software Engineering 2016, 2016

From reversible logic to quantum circuits: Logic design for an emerging technology.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Using \pi DDs for Nearest Neighbor Optimization of Quantum Circuits.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Checking Reversibility of Boolean Functions.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Ground setting properties for an efficient translation of OCL in SMT-based model finding.
Proceedings of the ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems, 2016

Integrating an SMT-Based ModelFinder into USE.
Proceedings of the 13th Workshop on Model-Driven Engineering, 2016

Towards a Catalog of Structural and Behavioral Verification Tasks for UML/OCL Models.
Proceedings of the Modellierung 2016, 2.-4. März 2016, Karlsruhe, 2016

Frame conditions in symbolic representations of UML/OCL models.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Fault Detection in Parity Preserving Reversible Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Logic Synthesis for Quantum State Generation.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Generating and checking control logic in the HDL-based design of reversible circuits.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Towards a model-based verification methodology for Complex Swarm Systems (Invited paper).
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

An improved gate library for logic synthesis of optical circuits.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

From biochips to quantum circuits: computer-aided design for emerging technologies.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Synthesis of approximate coders for on-chip interconnects using reversible logic.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Scalable One-Pass Synthesis for Digital Microfluidic Biochips.
IEEE Des. Test, 2015

Design of Microfluidic Biochips (Dagstuhl Seminar 15352).
Dagstuhl Reports, 2015

BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

Envisioning self-verification of electronic systems.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015

A Unified Formulation of Behavioral Semantics for SysML Models.
Proceedings of the MODELSWARD 2015, 2015

Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses.
Proceedings of the 12th Workshop on Model-Driven Engineering, 2015

Checking concurrent behavior in UML/OCL models.
Proceedings of the 18th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, 2015

Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification.
Proceedings of the Theory and Practice of Model Transformations, 2015

Formal Methods for Emerging Technologies.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A General and Exact Routing Methodology for Digital Microfluidic Biochips.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Reversible computation.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Leveraging the Analysis for Invariant Independence in Formal System Models.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Verification-Driven Design Across Abstraction Levels: A Case Study.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Contradiction Analysis for Inconsistent Formal Models.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Automated feature localization for dynamically generated SystemC designs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Assisted generation of frame conditions for formal models.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A generic representation of CCSL time constraints for UML/MARTE models.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Reverse BDD-based synthesis for splitter-free optical circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Considering nearest neighbor constraints of quantum circuits at the reversible circuit level.
Quantum Inf. Process., 2014

Introduction to the Special Issue on Reversible Computation.
ACM J. Emerg. Technol. Comput. Syst., 2014

Trading off circuit lines and gate costs in the synthesis of reversible logic.
Integr., 2014

Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models.
Proceedings of the Tests and Proofs - 8th International Conference, 2014

Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Validating SystemC Implementations Against Their Formal Specifications.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

RevVis: Visualization of Structures and Properties in Reversible Circuits.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Equivalence Checking in Multi-level Quantum Systems.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Towards a Base Model for UML and OCL Verification.
Proceedings of the 11th Workshop on Model-Driven Engineering, 2014

Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL.
Proceedings of the 2014 19th International Conference on Engineering of Complex Computer Systems, 2014

Exact routing for digital microfluidic biochips with temporary blockages.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automated and quality-driven requirements engineering.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automatic refinement checking for formal system models.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Verifying consistency between activity diagrams and their corresponding OCL contracts.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Optimizing DD-based synthesis of reversible circuits using negative control lines.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Exact One-pass Synthesis of Digital Microfluidic Biochips.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Optimal SWAP gate insertion for nearest neighbor quantum circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Efficient synthesis of quantum circuits implementing clifford group operations.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits.
J. Multiple Valued Log. Soft Comput., 2013

Clarification on the Mapping of Reversible Circuits to the NCV-v1 Library.
CoRR, 2013

On the "Q" in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-Structure.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Exploiting Negative Control Lines in the Optimization of Reversible Circuits.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Reducing the Depth of Quantum Circuits Using Additional Circuit Lines.
Proceedings of the Reversible Computation - 5th International Conference, 2013

The SyReC hardware description language: Enabling scalable synthesis of reversible circuits.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

PASSAT 2.0: A multi-functional SAT-based testing framework.
Proceedings of the 14th Latin American Test Workshop, 2013

Data extraction from SystemC designs using debug symbols and the SystemC API.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Exact Template Matching Using Boolean Satisfiability.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Improved SAT-based ATPG: more constraints, better compaction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung.
Proceedings of the 43. Jahrestagung der Gesellschaft für Informatik, 2013

Minimal Stimuli Generation in Simulation-Based Verification.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Cone of Influence Analysis at the Electronic System Level Using Machine Learning.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Towards a generic verification methodology for system models.
Proceedings of the Design, Automation and Test in Europe, 2013

Determining relevant model elements for the verification of UML/OCL specifications.
Proceedings of the Design, Automation and Test in Europe, 2013

Improving the mapping of reversible circuits to quantum circuits using multiple target lines.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Equivalence Checking of Reversible Circuits.
J. Multiple Valued Log. Soft Comput., 2012

RevKit: A Toolkit for Reversible Circuit Design.
J. Multiple Valued Log. Soft Comput., 2012

Reducing Reversible Circuit Cost by Adding Lines.
J. Multiple Valued Log. Soft Comput., 2012

Foreword: Special Issue on Reversible Computation.
J. Multiple Valued Log. Soft Comput., 2012

Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper).
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Assisted Behavior Driven Development Using Natural Language Processing.
Proceedings of the Objects, Models, Components, Patterns - 50th International Conference, 2012

Using <i>π</i>DDs in the Design of Reversible Circuits.
Proceedings of the Reversible Computation, 4th International Workshop, 2012

Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams.
Proceedings of the Reversible Computation, 4th International Workshop, 2012

Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

A Synthesis Flow for Sequential Reversible Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Synthesis of Reversible Circuits Using Decision Diagrams.
Proceedings of the International Symposium on Electronic System Design, 2012

Generating formal system models from natural language descriptions.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Completeness-Driven Development.
Proceedings of the Graph Transformations - 6th International Conference, 2012

Formal Specification Level.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

Formal Specification Level: Towards verification-driven design based on natural language processing.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Coverage-Driven Stimuli Generation.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Debugging of inconsistent UML/OCL models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Automatic design of low-power encoders using reversible circuit synthesis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Eliminating invariants in UML/OCL models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Realizing reversible circuits using a new class of quantum gates.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Synthesis of reversible circuits with minimal lines for large functions.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Synthesis of quantum circuits for linear nearest neighbor architectures.
Quantum Inf. Process., 2011

Debugging reversible circuits.
Integr., 2011

Design of Reversible and Quantum Circuits (Dagstuhl Seminar 11502).
Dagstuhl Reports, 2011

Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models.
Proceedings of the Tests and Proofs - 5th International Conference, 2011

RevKit: An Open Source Toolkit for the Design of Reversible Circuits.
Proceedings of the Reversible Computation - Third International Workshop, 2011

Designing a RISC CPU in Reversible Logic.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Efficient realization of control logic in reversible circuits.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms.
Proceedings of the Applications of Evolutionary Computation, 2011

Determining the minimal number of lines for large reversible circuits.
Proceedings of the Design, Automation and Test in Europe, 2011

Verifying dynamic aspects of UML models.
Proceedings of the Design, Automation and Test in Europe, 2011

Improved Fault Diagnosis for Reversible Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Synthese reversibler Logik (Synthesizing Reversible Logic).
it Inf. Technol., 2010

BDD-Based Synthesis of Reversible Logic.
Int. J. Appl. Metaheuristic Comput., 2010

Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic.
Electron. Notes Theor. Comput. Sci., 2010

SyReC: A Programming Language for Synthesis of Reversible Circuits.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Efficient Simulation-Based Debugging of Reversible Logic.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

SAT-based ATPG for reversible circuits.
Proceedings of the 5th International Design and Test Workshop, 2010

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition.
Proceedings of the 5th International Design and Test Workshop, 2010

Enhancing debugging of multiple missing control errors in reversible logic.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Graph Transformation Units Guided by a SAT Solver.
Proceedings of the Graph Transformations - 5th International Conference, 2010

Window optimization of reversible and quantum circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Synthesizing multiplier in reversible logic.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Verifying UML/OCL models using Boolean satisfiability.
Proceedings of the Design, Automation and Test in Europe, 2010

Reducing the number of lines in reversible circuits.
Proceedings of the 47th Design Automation Conference, 2010

Towards a Design Flow for Reversible Logic.
Springer, ISBN: 978-90-481-9578-7, 2010

2009
Towards a design flow for reversible logic.
PhD thesis, 2009

Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Exact Synthesis of Elementary Quantum Gate Circuits.
J. Multiple Valued Log. Soft Comput., 2009

Reversible Logic Synthesis with Output Permutation.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Evaluation of Cardinality Constraints on SMT-Based Debugging.
Proceedings of the ISMVL 2009, 2009

Contradictory antecedent debugging in bounded model checking.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Ein Entwurfsablauf für Reversible Schaltkreise.
Proceedings of the Ausgezeichnete Informatikdissertationen 2009, 2009

SMT-based stimuli generation in the SystemC Verification library.
Proceedings of the Forum on specification and Design Languages, 2009

Synthesizing Reversible Circuits for Irreversible Functions.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Debugging of Toffoli networks.
Proceedings of the Design, Automation and Test in Europe, 2009

SWORD - Module-based SAT Solving.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

BDD-based synthesis of reversible logic for large functions.
Proceedings of the 46th Design Automation Conference, 2009

2008
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

RevLib: An Online Resource for Reversible Functions and Reversible Circuits.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Debugging Contradictory Constraints in Constraint-Based Random Simulation.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

Contradiction Analysis for Constraint-based Random Simulation.
Proceedings of the Forum on specification and Design Languages, 2008

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Quantified Synthesis of Reversible Logic.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
SWORD: A SAT like prover using word level information.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Formal Verification on the Word Level using SAT-like Proof Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Fast exact Toffoli network synthesis of reversible logic.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

1993
The chaos router chip: design and implementation of an adaptive router.
Proceedings of the VLSI 93, 1993


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