D. Michael Miller

According to our database, D. Michael Miller authored at least 93 papers between 1976 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Function translations and search-based transformation for MVL reversible circuit synthesis.

D. Michael Miller, Gerhard W. Dueck

Sci. Comput. Program., 2021

Descending Order Transformation-based Synthesis of MVL Reversible Circuits.

D. Michael Miller, Gerhard W. Dueck

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

2020

A Spectral Algorithm for 3-valued Function Equivalence Classification.

D. Michael Miller, Mathias Soeken

J. Multiple Valued Log. Soft Comput., 2020

Search-Based Transformation Synthesis for 3-Valued Reversible Circuits.

D. Michael Miller, Gerhard W. Dueck

Proceedings of the Reversible Computation - 12th International Conference, 2020

Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms.

Kaitlin N. Smith, Mitchell A. Thornton, D. Michael Miller

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2019

A Hybrid Method for Spectral Translation Equivalent Boolean Functions.

Mathias Soeken, Eleonora Testa, D. Michael Miller

Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

2018

A Spectral Algorithm for Ternary Function Classification.

D. Michael Miller, Mathias Soeken

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2016

QMDDs: Efficient Quantum Function Representation and Manipulation.

Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Embedding of Large Boolean Functions for Reversible Logic.

Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler

ACM J. Emerg. Technol. Comput. Syst., 2016

Using SPIN to Check Simulink Stateflow Models.

Chikatoshi Yamada, D. Michael Miller

Int. J. Networked Distributed Comput., 2016

A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis.

Mathias Soeken, Gerhard W. Dueck, D. Michael Miller

Proceedings of the Reversible Computation - 8th International Conference, 2016

An extension of transformation-based reversible and quantum circuit synthesis.

Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Self-Inverse Functions and Palindromic Circuits.

Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller

CoRR, 2015

Using SPIN to Check Nondeterministic Simulink Stateflow Models.

Chikatoshi Yamada, D. Michael Miller

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Using QMDD in Numerical Methods for Solving Linear Differential Equations via Walsh Functions.

Radomir S. Stankovic, D. Michael Miller

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014

Reversible, Information-Preserving Logic and Its Application.

Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller

J. Multiple Valued Log. Soft Comput., 2014

Trading off circuit lines and gate costs in the synthesis of reversible logic.

Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler

Integr., 2014

Mapping NCV Circuits to Optimized Clifford+T Circuits.

D. Michael Miller, Mathias Soeken, Rolf Drechsler

Proceedings of the Reversible Computation - 6th International Conference, 2014

2013

On quantum circuits employing roots of the Pauli matrices.

Mathias Soeken, D. Michael Miller, Rolf Drechsler

CoRR, 2013

Clarification on the Mapping of Reversible Circuits to the NCV-v1 Library.

Zahra Sasanian, Robert Wille, D. Michael Miller

CoRR, 2013

2012

Synthesis of Semi-Classical Quantum Circuits.

Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller

J. Multiple Valued Log. Soft Comput., 2012

Equivalence Checking of Reversible Circuits.

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler

J. Multiple Valued Log. Soft Comput., 2012

Mapping a Multiple-control Toffoli Gate Cascade to an Elementary Quantum Gate Circuit.

Zahra Sasanian, D. Michael Miller

J. Multiple Valued Log. Soft Comput., 2012

Reducing Reversible Circuit Cost by Adding Lines.

D. Michael Miller, Robert Wille, Rolf Drechsler

J. Multiple Valued Log. Soft Comput., 2012

High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation?

Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski

J. Multiple Valued Log. Soft Comput., 2012

Reversible and Quantum Circuit Optimization: A Functional Approach.

Zahra Sasanian, D. Michael Miller

Proceedings of the Reversible Computation, 4th International Workshop, 2012

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits.

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries.

D. Michael Miller, Zahra Sasanian

Proceedings of the International Symposium on Electronic System Design, 2012

Realizing reversible circuits using a new class of quantum gates.

Zahra Sasanian, Robert Wille, D. Michael Miller

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Transforming MCT Circuits to NCVW Circuits.

Zahra Sasanian, D. Michael Miller

Proceedings of the Reversible Computation - Third International Workshop, 2011

Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates.

D. Michael Miller, Robert Wille, Zahra Sasanian

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation.

Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010

Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups.

Stanislav Stankovic, Jaakko Astola, D. Michael Miller, Radomir S. Stankovic

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

2009

Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics.

David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller

J. Multiple Valued Log. Soft Comput., 2009

A Heterogeneous Decision Diagram Package.

D. Michael Miller, Radomir S. Stankovic

Proceedings of the Computer Aided Systems Theory, 2009

Synthesizing Reversible Circuits for Irreversible Functions.

D. Michael Miller, Robert Wille, Gerhard W. Dueck

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Quantum Circuit Simplification and Level Compaction.

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction.

Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Quantum Logic Implementation of Unary Arithmetic Operations.

Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams.

David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits.

David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller

Proceedings of the Design, Automation and Test in Europe, 2008

An efficient verification of quantum circuits under a practical restriction.

Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller

Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

Multiple Valued Logic - Concepts and Representations.

D. Michael Miller, Mitchell Aaron Thornton

Synthesis lectures on digital circuits and systems 12, Morgan & Claypool Publishers, ISBN: 978-1-59829-190-2, 2008

2007

Multiple Valued Logic: Concepts and Representations

D. Michael Miller, Mitchell A. Thornton

Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79779-8, 2007

Techniques for the synthesis of reversible Toffoli networks.

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller

ACM Trans. Design Autom. Electr. Syst., 2007

QMDD Minimization Using Sifting for Variable Reordering.

D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton

J. Multiple Valued Log. Soft Comput., 2007

Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits.

Dmitri Maslov, D. Michael Miller

IET Comput. Digit. Tech., 2007

Variable Reordering and Sifting for QMDD.

D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006

Synthesis of Quantum Multiple-Valued Circuits.

D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck

J. Multiple Valued Log. Soft Comput., 2006

QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits.

D. Michael Miller, Mitchell A. Thornton

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

A Decision Diagram Package for Reversible and Quantum Circuit Simulation.

D. Michael Miller, Mitchell A. Thornton, David Goodman

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2005

Synthesis of Fredkin-Toffoli reversible networks.

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller

IEEE Trans. Very Large Scale Integr. Syst., 2005

Toffoli network synthesis with templates.

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Quantum Circuit Simplification Using Templates.

Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck

Proceedings of the 2005 Design, 2005

2004

Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs.

Mitchell A. Thornton, D. Michael Miller

J. Multiple Valued Log. Soft Comput., 2004

A Synthesis Method for MVL Reversible Logi.

D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Introduction: Special Issue in Recognition of Kenneth C. Smith.

Ali Sheikholeslami, D. Michael Miller

J. Multiple Valued Log. Soft Comput., 2003

Simplification of Toffoli Networks via Templates.

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Augmented Sifting of Multiple-Valued Decision Diagrams.

D. Michael Miller, Rolf Drechsler

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

On the Size of Multiple-Valued Decision Diagrams.

D. Michael Miller, Gerhard W. Dueck

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Fredkin/Toffoli Templates for Reversible Logic Synthesis.

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A transformation based algorithm for reversible logic synthesis.

D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck

Proceedings of the 40th Design Automation Conference, 2003

2002

Multi-Output Timed Shannon Circuits.

Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Chrestenson Spectrum Computation Using Cayley Color Graphs.

Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

On the Construction of Multiple-Valued Decision Diagrams.

D. Michael Miller, Rolf Drechsler

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations.

Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

Spectral techniques in VLSI CAD.

Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller

Kluwer, ISBN: 978-0-7923-7433-6, 2001

2000

Logic Synthesis of Controllers for B-Ternary Asynchronous Systems.

Yasunori Nagata, D. Michael Miller, Masao Mukaidono

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

TOP: An Algorithm for Three-Level Optimization of PLDs.

Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio

Proceedings of the 2000 Design, 2000

1999

B-ternary Logic Based Asynchronous Micropipeline.

Yasunori Nagata, D. Michael Miller, Masao Mukaidono

Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

1998

An improved method for computing a generalized spectral coefficient.

D. Michael Miller

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs.

Yasunori Nagata, D. Michael Miller, Masao Mukaidono

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Implementing a Multiple-Valued Decision Diagram Package.

D. Michael Miller, Rolf Drechsler

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1996

Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping".

Shujian Zhang, D. Michael Miller, Jon C. Muzio

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs.

Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

Multiple-Valued Decision Diagrams with Symmetric Variable Nodes.

D. Michael Miller, Noriaki Muranaka

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

A spectral method for Boolean function matching.

D. Michael Miller

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults.

Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller

J. Electron. Test., 1995

1994

Spectral Transformation of Multiple-Valued Decision Diagrams.

D. Michael Miller

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults.

Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Decimal Addition and Subtraction Units Using the <i>p</i>-Valued Decimal Signed-Digit Number Representation.

Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

Multiple-Valued Logic Design Tools.

D. Michael Miller

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

1992

The OR-k method for on-line checking of programmable logic arrays.

D. M. Marcynuk, D. Michael Miller

J. Electron. Test., 1992

Autocorrelation Techniques for Multi-Bit Decoder PLAs.

Randal Tomczuk, D. Michael Miller

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

BIST Generators for Sequential Faults.

Shujian Zhang, Rod Byrne, D. Michael Miller

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1990

The analysis of one-dimensional linear cellular automata and their aliasing properties.

Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

RCM-MVL: A Recursive Consensus MVL Minimization Algorithm.

Gerhard W. Dueck, D. Michael Miller

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

Estimating aliasing in CA and LFSR based signature registers.

D. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

Cellular automata-based pseudorandom number generators for built-in self-test.

Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. Michael Miller, Howard C. Card

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1984

Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks.

D. Michael Miller, Jon C. Muzio

IEEE Trans. Computers, 1984

1983

Spectral Fault Signatures for Internally Unate Combinational Networks.

D. Michael Miller, Jon C. Muzio

IEEE Trans. Computers, 1983

1980

A class of two-place three-valued unary generators.

D. Michael Miller, Jon C. Muzio

Notre Dame J. Formal Log., 1980

1976

A ternary universal decision element.

D. Michael Miller, Jon C. Muzio

Notre Dame J. Formal Log., 1976