Mathias Soeken

According to our database1, Mathias Soeken authored at least 168 papers between 2008 and 2020.

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Bibliography

2020
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Advanced Functional Decomposition Using Majority and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Enabling accuracy-aware Quantum compilers using symbolic resource estimation.
Proc. ACM Program. Lang., 2020

A Spectral Algorithm for 3-valued Function Equivalence Classification.
J. Multiple Valued Log. Soft Comput., 2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.
IACR Cryptol. ePrint Arch., 2020

Determining the Multiplicative Complexity of Boolean Functions using SAT.
IACR Cryptol. ePrint Arch., 2020

Improved Quantum Circuits for Elliptic Curve Discrete Logarithms.
IACR Cryptol. ePrint Arch., 2020

Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks.
CoRR, 2020

Automatic accuracy management of quantum programs via (near-)symbolic resource estimation.
CoRR, 2020

Extending Boolean Methods for Scalable Logic Synthesis.
IEEE Access, 2020

Quantum Circuits for Functionally Controlled NOT Gates.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2020

Symbolic Algorithms for Token Swapping.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Automatic Uniform Quantum State Preparation Using Decision Diagrams.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Enumerating Optimal Quantum Circuits using Spectral Classification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Exact DAG-Aware Rewriting.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
LUT-Based Hierarchical Reversible Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Mapping Monotone Boolean Functions into Majority.
IEEE Trans. Computers, 2019

Logic Synthesis for Established and Emerging Computing.
Proc. IEEE, 2019

ROS: Resource-constrained Oracle Synthesis for Quantum Computers.
Proceedings of the Proceedings 16th International Conference on Quantum Physics and Logic, 2019

Using ZDDs in the mapping of quantum circuits.
Proceedings of the Proceedings 16th International Conference on Quantum Physics and Logic, 2019

A Hybrid Method for Spectral Translation Equivalent Boolean Functions.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Logic Optimization of Majority-Inverter Graphs.
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Scaling-up ESOP Synthesis for Quantum Compilation.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Exact Synthesis of Boolean Functions in Majority-of-Five Forms.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits.
Proceedings of the International Conference on Computer-Aided Design, 2019

Scalable Boolean Methods in a Modern Synthesis Flow.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Compiling Permutations for Superconducting QPUs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reversible Pebbling Game for Quantum Memory Management.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Structural rewriting in XOR-majority graphs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Logic Synthesis for RRAM-Based In-Memory Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Behaviour Driven Development for Hardware Design.
IPSJ Trans. Syst. LSI Des. Methodol., 2018

Pairs of majority-decomposing functions.
Inf. Process. Lett., 2018

The complexity of error metrics.
Inf. Process. Lett., 2018

The EPFL Logic Synthesis Libraries.
CoRR, 2018

SAT-based {CNOT, T} Quantum Circuit Synthesis.
Proceedings of the Reversible Computation - 10th International Conference, 2018

Quantum Circuits for Floating-Point Arithmetic.
Proceedings of the Reversible Computation - 10th International Conference, 2018

Size Optimization of MIGs with an Application to QCA and STMG Technologies.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Spectral Algorithm for Ternary Function Classification.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Translating Between the Roots of the Identity in Quantum Computers.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Deep Learning for Logic Optimization Algorithms.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Integrated ESOP Refactoring for Industrial Designs.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Majority logic synthesis.
Proceedings of the International Conference on Computer-Aided Design, 2018

Practical exact synthesis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Programming quantum computers using design automation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improvements to boolean resynthesis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Canonical computation without canonical representation.
Proceedings of the 55th Annual Design Automation Conference, 2018

SAT based exact synthesis using DAG topology families.
Proceedings of the 55th Annual Design Automation Conference, 2018

A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Functional decomposition using majority.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Exact Synthesis of Majority-Inverter Graphs and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

metaSMT: focus on your application and not on solver integration.
Int. J. Softw. Tools Technol. Transf., 2017

Logic Synthesis for Quantum Computing.
CoRR, 2017

A PLiM Computer for the Internet of Things.
Computer, 2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Classifying Functions with Exact Synthesis.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

RM3 based logic synthesis (Special session paper).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Enabling exact delay synthesis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

An adaptive prioritized <i>ε</i>-preferred evolutionary algorithm for approximate BDD optimization.
Proceedings of the Genetic and Evolutionary Computation Conference, 2017

Wave pipelining for majority-based beyond-CMOS technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Design automation and design space exploration for quantum computers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Busy man's synthesis: Combinational delay optimization with SAT.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Endurance management for resistive Logic-In-Memory computing architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hierarchical Reversible Logic Synthesis Using LUTs.
Proceedings of the 54th Annual Design Automation Conference, 2017

A novel basis for logic rewriting.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Multi-level logic benchmarks: An exactness study.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Complexity of reversible circuits and their quantum implementations.
Theor. Comput. Sci., 2016

Ancilla-free synthesis of large reversible functions using binary decision diagrams.
J. Symb. Comput., 2016

Embedding of Large Boolean Functions for Reversible Logic.
ACM J. Emerg. Technol. Comput. Syst., 2016

SyReC: A hardware description language for the specification and synthesis of reversible circuits.
Integr., 2016

Verifying the structure and behavior in UML/OCL models using satisfiability solvers.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Enumeration of Reversible Functions and Its Application to Circuit Complexity.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Inversion optimization in Majority-Inverter Graphs.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Symbolic Error Metric Determination for Approximate Computing.
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016

Dynamic NoC buffer allocation for MPSoC timing side channel attack protection.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Notes on Majority Boolean Algebra.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

An extension of transformation-based reversible and quantum circuit synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Multilevel design understanding: from specification to logic (invited paper).
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Approximation-aware rewriting of AIGs for error tolerant applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

SAT-Based Combinational and Sequential Dependency Computation.
Proceedings of the Hardware and Software: Verification and Testing, 2016

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm.
Proceedings of the Genetic and Evolutionary Computation Conference, 2016

Fast hierarchical NPN classification.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Equivalence checking using Gröbner bases.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Multi-objective BDD optimization for RRAM based circuit design.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Optimizing Majority-Inverter Graphs with functional hashing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Formal verification of integer multipliers by combining Gröbner basis with logic reduction.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An MIG-based compiler for programmable logic-in-memory architectures.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Precise error determination of approximated components in sequential circuits with model checking.
Proceedings of the 53rd Annual Design Automation Conference, 2016

BDD minimization for approximate computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Specification-driven model transformation testing.
Softw. Syst. Model., 2015

Self-Inverse Functions and Palindromic Circuits.
CoRR, 2015

Reversible circuit rewriting with simulated annealing.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Coverage of OCL Operation Specifications and Invariants.
Proceedings of the Tests and Proofs - 9th International Conference, 2015

Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and Its Permutation Semantics.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses.
Proceedings of the 12th Workshop on Model-Driven Engineering, 2015

Fredkin-Enabled Transformation-Based Reversible Logic Synthesis.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Dynamic Template Matching with Mixed-Polarity Toffoli Gates.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Multi-Objective BDD Optimization with Evolutionary Algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference, 2015

Reverse Engineering with Simulation Graphs.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Requirement Phrasing Assistance Using Automatic Quality Assessment.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Formal Specification Level - Concepts, Methods, and Algorithms.
Springer, ISBN: 978-3-319-08698-9, 2015

2014
Upper bounds for reversible circuits based on Young subgroups.
Inf. Process. Lett., 2014

Trading off circuit lines and gate costs in the synthesis of reversible logic.
Integr., 2014

A framework for reversible circuit complexity.
CoRR, 2014

Behaviour Driven Development for Tests and Verification.
Proceedings of the Tests and Proofs - 8th International Conference, 2014

iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries.
Proceedings of the 8th International Workshop on Semantic Evaluation, 2014

Self-Verification as the Key Technology for Next Generation Electronic Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Mapping NCV Circuits to Optimized Clifford+T Circuits.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Quantum Circuit Optimization by Hadamard Gate Reduction.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Formale Methoden für Alle.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0".
Proceedings of the Advances in Production Management Systems. Innovative and Knowledge-Based Production Management in a Global-Local World, 2014

Automated and quality-driven requirements engineering.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automating the translation of assertions using natural language processing techniques.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

MetaSMT: a unified interface to SMT-LIB2.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2013
Formal specification level: concepts, methods, and algorithms.
PhD thesis, 2013

Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits.
J. Multiple Valued Log. Soft Comput., 2013

On quantum circuits employing roots of the Pauli matrices.
CoRR, 2013

White Dots do Matter: Rewriting Reversible Logic Circuits.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Reducing the Depth of Quantum Circuits Using Additional Circuit Lines.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Debugging of Reversible Circuits Using pDDs.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Exact Template Matching Using Boolean Satisfiability.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Grammar-based program generation based on model finding.
Proceedings of the 8th International Design and Test Symposium, 2013

Towards automatic scenario generation from coverage information.
Proceedings of the 8th International Workshop on Automation of Software Test, 2013

Formale Spezifikationsebene.
Proceedings of the Ausgezeichnete Informatikdissertationen 2013, 2013

Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung.
Proceedings of the 43. Jahrestagung der Gesellschaft für Informatik, 2013

Hardware-Software Co-Visualization: Developing systems in the holodeck.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Towards a generic verification methodology for system models.
Proceedings of the Design, Automation and Test in Europe, 2013

Determining relevant model elements for the verification of UML/OCL specifications.
Proceedings of the Design, Automation and Test in Europe, 2013

Improving the mapping of reversible circuits to quantum circuits using multiple target lines.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
RevKit: A Toolkit for Reversible Circuit Design.
J. Multiple Valued Log. Soft Comput., 2012

Assisted Behavior Driven Development Using Natural Language Processing.
Proceedings of the Objects, Models, Components, Patterns - 50th International Conference, 2012

Using <i>π</i>DDs in the Design of Reversible Circuits.
Proceedings of the Reversible Computation, 4th International Workshop, 2012

Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams.
Proceedings of the Reversible Computation, 4th International Workshop, 2012

Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

A Synthesis Flow for Sequential Reversible Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Behavior Driven Development for circuit design and verification.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Completeness-Driven Development.
Proceedings of the Graph Transformations - 6th International Conference, 2012

Formal Specification Level.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

Formal Specification Level: Towards verification-driven design based on natural language processing.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Debugging of inconsistent UML/OCL models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Eliminating invariants in UML/OCL models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Synthesis of reversible circuits with minimal lines for large functions.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models.
Proceedings of the Tests and Proofs - 5th International Conference, 2011

RevKit: An Open Source Toolkit for the Design of Reversible Circuits.
Proceedings of the Reversible Computation - Third International Workshop, 2011

Designing a RISC CPU in Reversible Logic.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Automatic property generation for the formal verification of bus bridges.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Verifying dynamic aspects of UML models.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition.
Proceedings of the 5th International Design and Test Workshop, 2010

Window optimization of reversible and quantum circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Verifying UML/OCL models using Boolean satisfiability.
Proceedings of the Design, Automation and Test in Europe, 2010

Reducing the number of lines in reversible circuits.
Proceedings of the 47th Design Automation Conference, 2010

2008
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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