Mehrtash Manoochehri

According to our database, Mehrtash Manoochehri authored at least 7 papers between 2009 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Accurate Model for Application Failure Due to Transient Faults in Caches.

Mehrtash Manoochehri, Michel Dubois

IEEE Trans. Computers, 2016

2015

Chip-independent Error Correction in main memories.

Mehrtash Manoochehri, Michel Dubois

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

2014

Extremely Low Cost Error Protection with Correctable Parity Protected Cache.

Mehrtash Manoochehri, Murali Annavaram, Michel Dubois

IEEE Trans. Computers, 2014

2011

Soft error benchmarking of L2 caches with PARMA.

Jinho Suh, Mehrtash Manoochehri, Murali Annavaram, Michel Dubois

Proceedings of the SIGMETRICS 2011, 2011

CPPC: correctable parity protected cache.

Mehrtash Manoochehri, Murali Annavaram, Michel Dubois

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2009

Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off.

Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies.

Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi

Proceedings of the The Forth International Conference on Availability, 2009