Meilin Liu

According to our database1, Meilin Liu authored at least 42 papers between 2004 and 2018.

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Bibliography

2018
BAVP: Blockchain-Based Access Verification Protocol in LEO Constellation Using IBE Keys.
Security and Communication Networks, 2018

2017
A Distributed Authentication Protocol Using Identity-Based Encryption and Blockchain for LEO Network.
Proceedings of the Security, Privacy, and Anonymity in Computation, Communication, and Storage, 2017

A-MapCG: An Adaptive MapReduce Framework for GPUs.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

2016
A Distributed Algorithm for Self-adaptive Routing in LEO Satellite Network.
SINC, 2016

Compile-Time Automatic Synchronization Insertion and Redundant Synchronization Elimination for GPU Kernels.
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016

2015
LSRB-CSR: A Low Overhead Storage Format for SpMV on the GPU Systems.
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015

2014
A Task Allocation Schema Based on Response Time Optimization in Cloud Computing.
CoRR, 2014

A Non-Cooperative Game Model for Reliability-Based Task Scheduling in Cloud Computing.
CoRR, 2014

2013
An Optimized GP-GPU Warp Scheduling Algorithm for Sparse Matrix-Vector Multiplication.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

On the complexity of undominated core and farsighted solution concepts in coalitional games.
Proceedings of the International conference on Autonomous Agents and Multi-Agent Systems, 2013

Planning with Multi-Valued Landmarks.
Proceedings of the Twenty-Seventh AAAI Conference on Artificial Intelligence, 2013

2012
General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size.
I. J. Comput. Appl., 2012

Overlapping Community Detection via Leader-Based Local Expansion in Social Networks.
Proceedings of the IEEE 24th International Conference on Tools with Artificial Intelligence, 2012

2011
Loop Distribution and Fusion with Timing and Code Size Optimization.
Signal Processing Systems, 2011

Detecting Link Communities Based on Local Approach.
Proceedings of the IEEE 23rd International Conference on Tools with Artificial Intelligence, 2011

Optimizing Memory Cost with Loop Transformations.
Proceedings of the ISCA 26th International Conference on Computers and Their Applications, 2011

2010
Variable Length Pattern Matching for Hardware Network Intrusion Detection System.
Signal Processing Systems, 2010

2009
Optimizing parallelism for nested loops with iterational and instructional retiming.
J. Embedded Computing, 2009

Energy minimization for heterogeneous wireless sensor networks.
J. Embedded Computing, 2009

Loop Fusion Technique with Minimal Memory Cost via Retiming.
Proceedings of the ISCA 24th International Conference on Computers and Their Applications, 2009

2008
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP.
J. Parallel Distrib. Comput., 2008

2007
Parallel Network Intrusion Detection on Reconfigurable Platforms.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

2006
Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units.
IEEE Trans. on Circuits and Systems, 2006

Design optimization and space minimization considering timing and code size via retiming and unfolding.
Microprocessors and Microsystems, 2006

Algorithms and analysis of scheduling for loops with minimum switching.
IJCSE, 2006

Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Loop Striping: Maximize Parallelism for Nested Loops.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Optimizing Timing and Code Size Using Maximum Direct Loop Fusion.
Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems, 2006

2005
Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005

Optimizing Nested Loops with Iterational and Instructional Retiming.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Iterational retiming: maximize iteration-level parallelism for nested loops.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Multi-level Loop Fusion with Minimal Code Size.
Proceedings of the ISCA 18th International Conference on Parallel and Distributed Computing Systems, 2005

A Feasible Baseline Architecture for Building and Evaluating Distributed Systems.
Proceedings of the ISCA 18th International Conference on Parallel and Distributed Computing Systems, 2005

2004
Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.
Proceedings of the Embedded and Ubiquitous Computing, 2004

General loop fusion technique for nested loops considering timing and code size.
Proceedings of the 2004 International Conference on Compilers, 2004

Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Loop Fusion via Retiming for DSP Applications.
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004


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