Qingfeng Zhuge

According to our database1, Qingfeng Zhuge
  • authored at least 147 papers between 2001 and 2018.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2018
Towards the Design of Efficient and Consistent Index Structure with Minimal Write Activities for Non-Volatile Memory.
IEEE Trans. Computers, 2018

Synthesizing distributed pipelining systems with timing constraints via optimal functional unit assignment and communication selection.
J. Comput. Science, 2018

On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core Assignment.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Efficient wear leveling for inodes of file systems on persistent memories.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Optimal Functional-Unit Assignment for Heterogeneous Systems Under Timing Constraint.
IEEE Trans. Parallel Distrib. Syst., 2017

Refinery swap: An efficient swap mechanism for hybrid DRAM-NVM systems.
Future Generation Comp. Syst., 2017

Efficient assignment algorithms to minimize operation cost for supply chain networks in agile manufacturing.
Computers & Industrial Engineering, 2017

BOSS: An Efficient Data Distribution Strategy for Object Storage Systems With Hybrid Devices.
IEEE Access, 2017

Towards the design of optimal range assignment for elevator groups under fluctuant traffic loads.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

Improving read performance via selective Vpass reduction on high density 3D NAND flash memory.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

UDORN: A design framework of persistent in-memory key-value database for NVM.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Optimal functional unit assignment and voltage selection for pipelined MPSoC with guaranteed probability on time performance.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

An Efficient Racetrack Memory-Based Processing-in-Memory Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Efficient Task Assignment and Scheduling on MPSOC with STT-RAM Based Hybrid SPMs Considering Data Allocation.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Improving LDPC performance via asymmetric sensing level placement on flash memory.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput.
Signal Processing Systems, 2016

Data Allocation with Minimum Cost under Guaranteed Probability for Multiple Types of Memories.
Signal Processing Systems, 2016

Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory.
IEEE Trans. VLSI Syst., 2016

Quality-of-Experience-Oriented Autonomous Intersection Control in Vehicular Networks.
IEEE Trans. Intelligent Transportation Systems, 2016

A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A New Design of In-Memory File System Based on File Virtual Address Framework.
IEEE Trans. Computers, 2016

Write reconstruction for write throughput improvement on MLC PCM based main memory.
Journal of Systems Architecture - Embedded Systems Design, 2016

A unified framework for designing high performance in-memory and hybrid memory file systems.
Journal of Systems Architecture - Embedded Systems Design, 2016

A Convex Optimization Based Autonomous Intersection Control Strategy in Vehicular Cyber-Physical Systems.
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

Performance Optimization for In-Memory File Systems on NUMA Machines.
Proceedings of the 17th International Conference on Parallel and Distributed Computing, 2016

The design and implementation of an efficient user-space in-memory file system.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Towards Real-Time and Temporal Information Services in Vehicular Networks via Multi-Objective Optimization.
Proceedings of the 41st IEEE Conference on Local Computer Networks, 2016

Optimizing Data Placement of MapReduce on Ceph-Based Framework under Load-Balancing Constraint.
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016

Optimal Functional Assignment and Communication Selection under Timing Constraint for Self-Timed Pipelines.
Proceedings of the 13th International Conference on Embedded Software and Systems, 2016

The Design and Implementation of an Efficient Data Consistency Mechanism for In-Memory File Systems.
Proceedings of the 13th International Conference on Embedded Software and Systems, 2016

Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory.
Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016

The design of an efficient swap mechanism for hybrid DRAM-NVM systems.
Proceedings of the 2016 International Conference on Embedded Software, 2016

Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Optimal functional-unit assignment and buffer placement for probabilistic pipelines.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

The Design and Implementation of a High-Performance Hybrid Memory File System.
Proceedings of the International Conference on Advanced Cloud and Big Data, 2016

Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint.
Signal Processing Systems, 2015

Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems.
IEEE Trans. VLSI Syst., 2015

Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs.
IEEE Trans. Parallel Distrib. Syst., 2015

Power Efficiency for Hardware/Software Partitioning with Time and Area Constraints on MPSoC.
International Journal of Parallel Programming, 2015

Designing an efficient persistent in-memory file system.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Improving MLC PCM write throughput by write reconstruction.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Vehicle Assisted Data Update for Temporal Information Service in Vehicular Networks.
Proceedings of the IEEE 18th International Conference on Intelligent Transportation Systems, 2015

Efficient Scheduling with Intensive In-Memory File Accesses Considering Bandwidth Constraint on Memory Bus.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

Prevent Deadlock and Remove Blocking for Self-Timed Systems.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

nCode: limiting harmful writes to emerging mobile NVRAM through code swapping.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Maximizing IO performance via conflict reduction for flash memory storage systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Area and performance co-optimization for domain wall memory in application-specific embedded systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Optimizing data placement for reducing shift operations on domain wall memories.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Minimizing System Cost with Efficient Task Assignment on Heterogeneous Multicore Processors Considering Time Constraint.
IEEE Trans. Parallel Distrib. Syst., 2014

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors.
ACM Trans. Embedded Comput. Syst., 2014

Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories.
IEEE Trans. Computers, 2014

A space allocation and reuse strategy for PCM-based embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2014

A Partition-based Mechanism for Reducing Energy in Phase Change Memory.
JCP, 2014

Optimizing Data Distribution for Loops on Embedded Multicore with Scratch-Pad Memory.
JCP, 2014

Efficient fault-tolerant scheduling on multiprocessor systems via replication and deallocation.
IJES, 2014

Efficient grouping-based mapping and scheduling on heterogeneous cluster architectures.
Computers & Electrical Engineering, 2014

Contention-aware task and communication co-scheduling for network-on-chip based Multiprocessor System-on-Chip.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Non-volatile registers aware instruction selection for embedded systems.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Wear-leveling for PCM main memory on embedded system via page management and process scheduling.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Energy efficient routing techniques with guaranteed reliability based on multi-level uncertain graph.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

On self-timed ring for consistent mapping and maximum throughput.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Minimum-cost data allocation with guaranteed probability on multiple types of memory.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Joint Convergecast and Power Allocation in Wireless Sensor Networks.
Proceedings of the 15th International Conference on Parallel and Distributed Computing, 2014

2013
Optimizing Data Placement of Loops for Energy Minimization with Multiple Types of Memories.
Signal Processing Systems, 2013

Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory.
Signal Processing Systems, 2013

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory.
IEEE Trans. VLSI Syst., 2013

Write activity reduction on non-volatile main memories for embedded chip multiprocessors.
ACM Trans. Embedded Comput. Syst., 2013

Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory.
Journal of Systems Architecture - Embedded Systems Design, 2013

Accurate age counter for wear leveling on non-volatile based main memory.
Design Autom. for Emb. Sys., 2013

A content-aware writing mechanism for reducing energy on non-volatile memory based embedded storage systems.
Design Autom. for Emb. Sys., 2013

Effective file data-block placement for different types of page cache on hybrid main memory architectures.
Design Autom. for Emb. Sys., 2013

Optimal data allocation algorithm for loop-centric applications on scratch-PAD memories.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Optimizing task assignment for heterogeneous multiprocessor system with guaranteed reliability and timing constraint.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

A space-based wear leveling for PCM-based embedded systems.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Efficient task assignment and scheduling for MPSoC DSPS with VS-SPM considering concurrent accesses through data allocation.
Proceedings of the IEEE International Conference on Acoustics, 2013

Software enabled wear-leveling for hybrid PCM main memory on embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Minimizing Access Cost for Multiple Types of Memory Units in Embedded Systems Through Data Allocation and Scheduling.
IEEE Trans. Signal Processing, 2012

Memory access schedule minimization for embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2012

General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size.
I. J. Comput. Appl., 2012

Optimizing Data Allocation for Loops on Embedded Systems with Scratch-Pad Memory.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Optimal Assignment for Tree-Structure Task Graph on Heterogeneous Multicore Systems Considering Time Constraint.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Loop scheduling optimization for chip-multiprocessors with non-volatile main memory.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Efficient Task Assignment on Heterogeneous Multicore Systems Considering Communication Overhead.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

PRR: A low-overhead cache replacement algorithm for embedded processors.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Loop Distribution and Fusion with Timing and Code Size Optimization.
Signal Processing Systems, 2011

Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Variable assignment and instruction scheduling for processor with multi-module memory.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Optimal Data Placement for Memory Architectures with Scratch-Pad Memories.
Proceedings of the IEEE 10th International Conference on Trust, 2011

Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-core Systems.
Proceedings of the International Conference on Parallel Processing, 2011

Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Variable Length Pattern Matching for Hardware Network Intrusion Detection System.
Signal Processing Systems, 2010

Algorithms for Optimally Arranging Multicore Memory Structures.
EURASIP J. Emb. Sys., 2010

Optimal scheduling to minimize non-volatile memory access time with hardware cache.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Minimizing write activities to non-volatile memory via scheduling and recomputation.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

2008
Timing optimization via nest-loop pipelining considering code size.
Microprocessors and Microsystems - Embedded Hardware Design, 2008

2007
Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks.
Computer Communications, 2007

Parallel Network Intrusion Detection on Reconfigurable Platforms.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

2006
Loop scheduling with timing and switching-activity minimization for VLIW DSP.
ACM Trans. Design Autom. Electr. Syst., 2006

Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units.
IEEE Trans. on Circuits and Systems, 2006

Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.
IEEE Trans. Computers, 2006

Design optimization and space minimization considering timing and code size via retiming and unfolding.
Microprocessors and Microsystems, 2006

Algorithms and analysis of scheduling for loops with minimum switching.
IJCSE, 2006

Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Efficient Assignment and Scheduling for Heterogeneous DSP Systems.
IEEE Trans. Parallel Distrib. Syst., 2005

Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005

Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.
Proceedings of the Embedded and Ubiquitous Computing, 2005

High-level synthesis for DSP applications using heterogeneous functional units.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Efficient variable partitioning and scheduling for DSP processors with multiple memory modules.
IEEE Trans. Signal Processing, 2004

Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking.
I. J. Comput. Appl., 2004

Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors.
IJHPCN, 2004

Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Dynamic Update of Shortest Path Tree in OSPF.
Proceedings of the 7th International Symposium on Parallel Architectures, 2004

Approximation Algorithms Design for Disk Partial Covering Problem.
Proceedings of the 7th International Symposium on Parallel Architectures, 2004

Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Timing Optimization of Nested Loops Considering Code Size for DSP Applications.
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

Dynamic shortest path tree update for multiple link state decrements.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.
Proceedings of the Embedded and Ubiquitous Computing, 2004

General loop fusion technique for nested loops considering timing and code size.
Proceedings of the 2004 International Conference on Compilers, 2004

Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Loop Fusion via Retiming for DSP Applications.
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004

2003
Code size reduction technique and implementation for software-pipelined DSP applications.
ACM Trans. Embedded Comput. Syst., 2003

An Integrated Framework of Design Optimization and Space Minimization for DSP applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Loop scheduling for minimizing schedule length and switching activities.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design space minimization with timing and code size optimization for embedded DSP.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Defending Embedded Systems Against Buffer Overflow via Hardware/Software.
Proceedings of the 19th Annual Computer Security Applications Conference (ACSAC 2003), 2003

Design and Analysis of Improved Shortest Path Tree Update for Network Routing.
Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003

2002
Analysis and Algorithms for Partitioning of Large-scale Adaptive Mobile Networks.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Performance optimization of multiple memory architectures for DSP.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

2001
Scheduling and partitioning for multiple loop nests.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Minimum dynamic update for shortest path tree construction.
Proceedings of the Global Telecommunications Conference, 2001

Efficient Update of Shortest Path Algorithms for Network Routing.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001


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