Chun Jason Xue

Proceedings of the 20th USENIX Conference on File and Storage Technologies, 2022

PipeDevice: a hardware-software co-design approach to intra-host container communication.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on emerging Networking EXperiments and Technologies, 2022

Lamina: Low Overhead Wear Leveling for NVM with Bounded Tail.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Combating Sampling Bias: A Self-Training Method in Credit Risk Models.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021

iTRIM: I/O-Aware TRIM for Improving User Experience on Mobile Devices.

[BibT_eX]

[DOI]

Cheng Ji

Chenchen Fu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Read-Ahead Efficiency on Mobile Devices: Observation, Characterization, and Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Accelerating data filtering for database using FPGA.

[BibT_eX]

[DOI]

J. Syst. Archit., 2021

NatiDroid: Cross-Language Android Permission Specification.

[BibT_eX]

[DOI]

CoRR, 2021

Bayesian Nested Neural Networks for Uncertainty Calibration and Adaptive Compression.

[BibT_eX]

[DOI]

CoRR, 2021

Composite Resource Scheduling for Networked Control Systems.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Keep Fresh: Real-Time Data Retrieval with Speed Adaptation in Mobile Cyber-Physical Systems.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Two-Dimensional Learning Rate Decay: Towards Accurate Federated Learning with Non-IID Data.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2021

How the common retention acceleration method of 3D NAND flash memory goes wrong?

[BibT_eX]

[DOI]

Proceedings of the HotStorage '21: 13th ACM Workshop on Hot Topics in Storage and File Systems, 2021

SFP: Smart File-Aware Prefetching for Flash based Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Pattern-Guided File Compression with User-Experience Enhancement for Log-Structured File System on Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021

MobileSwap: Cross-Device Memory Swapping for Mobile Devices.

[BibT_eX]

[DOI]

Changlong Li

Liang Shi

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Bayesian Nested Neural Networks for Uncertainty Calibration and Adaptive Compression.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State Drives.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

FlashEmbedding: storing embedding tables in SSD for large-scale recommender systems.

[BibT_eX]

[DOI]

Proceedings of the APSys '21: 12th ACM SIGOPS Asia-Pacific Workshop on Systems, 2021

2020

Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2020

Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

Inspection and Characterization of App File Usage in Mobile Devices.

[BibT_eX]

[DOI]

ACM Trans. Storage, 2020

Applying Multiple Level Cell to Non-volatile FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2020

Energy-Constrained Data Freshness Optimization in Self-Powered Networked Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Boosting User Experience via Foreground-Aware Cache Management in UFS Mobile Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Pruning Deep Reinforcement Learning for Dual User Experience and Storage Lifetime Improvement on Mobile Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SEAL: User Experience-Aware Two-Level Swap for Mobile Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Aging Capacitor Supported Cache Management Scheme for Solid-State Drives.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Maximizing I/O Throughput and Minimizing Performance Variation via Reinforcement Learning Based I/O Merging for SSDs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

Acclaim: Adaptive Memory Reclaim to Improve User Experience in Android Systems.

[BibT_eX]

[DOI]

Jinheng Li

Proceedings of the 2020 USENIX Annual Technical Conference, 2020

Maintaining Real-Time Data Freshness in Wireless Powered Communication Networks.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020

A Zero-Energy Consumption Scheme for System Suspend to Limited NVM.

[BibT_eX]

[DOI]

Proceedings of the 9th Non-Volatile Memory Systems and Applications Symposium, 2020

Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Fully Nested Neural Network for Adaptive Compression and Quantization.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020

FPGA-based Compaction Engine for Accelerating LSM-tree Key-Value Stores.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Data Engineering, 2020

Loop2Recursion: Compiler-Assisted Wear Leveling for Non-Volatile Memory.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Overcoming Memory Constraint for Improved Target Classification Performance on Embedded Deep Learning Systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020

Position: Synergetic effects of Software and Hardware Parameters on the LSM system.

[BibT_eX]

[DOI]

Proceedings of the 12th USENIX Workshop on Hot Topics in Storage and File Systems, 2020

Differentiating Cache Files for Fine-grain Management to Improve Mobile Performance and Lifetime.

[BibT_eX]

[DOI]

Jinheng Li

Xianzhang Chen

Riwei Pan

Tei-Wei Kuo

Proceedings of the 12th USENIX Workshop on Hot Topics in Storage and File Systems, 2020

Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Access Characteristic Guided Partition for Read Performance Improvement on Solid State Drives.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Using Small Business Banking Data for Explainable Credit Risk Scoring.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019

File Fragmentation in Mobile Devices: Measurement, Evaluation, and Treatment.

[BibT_eX]

[DOI]

IEEE Trans. Mob. Comput., 2019

A Hardware-Accelerated Solution for Hierarchical Index-Based Merge-Join.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 2019

Real-Time Data Retrieval in Cyber-Physical Systems with Temporal Validity and Data Availability Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 2019

Introduction to the Special Issue on Human-interaction-aware Data Analytics for Cyber-physical Systems.

[BibT_eX]

[DOI]

ACM Trans. Cyber Phys. Syst., 2019

Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

EMC: Energy-Aware Morphable Cache Design for Non-Volatile Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Boosting read-ahead efficiency for improved user experience on mobile devices.

[BibT_eX]

[DOI]

SIGBED Rev., 2019

BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors.

[BibT_eX]

[DOI]

Microelectron. J., 2019

A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices.

[BibT_eX]

[DOI]

IEEE Micro, 2019

luXbeacon - A Batteryless Beacon for Green IoT: Design, Modeling, and Field Tests.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2019

Accelerating Monte Carlo Bayesian Inference via Approximating Predictive Uncertainty over Simplex.

[BibT_eX]

[DOI]

CoRR, 2019

Checkpointing-aware Data Allocation for Energy Harvesting Powered Non-volatile Processors.

[BibT_eX]

[DOI]

Fuyang Li

Qing'an Li

Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

Optimizing Tail Latency of LDPC based Flash Memory Storage Systems Via Smart Refresh.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Conference on Networking, 2019

Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs.

[BibT_eX]

[DOI]

Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019

Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

1+1>2: variation-aware lifetime enhancement for embedded 3D NAND flash systems.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

Reinforcement Learning based Background Segment Cleaning for Log-structured File System on Mobile Devices.

[BibT_eX]

[DOI]

Chao Wu

Cheng Ji

Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

A Hardware-Accelerated Solution for Hierarchical Index-Based Merge-Join(Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International Conference on Data Engineering, 2019

Mismatched Memory Management of Android Smartphones.

[BibT_eX]

[DOI]

Qiao Li

Proceedings of the 11th USENIX Workshop on Hot Topics in Storage and File Systems, 2019

Sentinel Cells Enabled Fast Read for NAND Flash.

[BibT_eX]

[DOI]

Proceedings of the 11th USENIX Workshop on Hot Topics in Storage and File Systems, 2019

A Wear Leveling Aware Memory Allocator for Both Stack and Heap Management in PCM-based Main Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Online Rare Category Detection for Edge Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Transmit or Discard: Optimizing Data Freshness in Networked Embedded Systems with Energy Harvesting Sources.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Leveraging Approximate Data for Robust Flash Storage.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Wear-Leveling-Aware Fine-Grained Allocator for Non-Volatile Memory.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

PreGC: Pre-migrating valid pages to relieve performance cliff of 3D solid-state drives: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018

PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Introduction to the Special Issue on NVM and Storage.

[BibT_eX]

[DOI]

Mohammad Abdullah Al Faruque

Michael M. Swift

ACM Trans. Storage, 2018

Avoiding Data Inconsistency in Energy Harvesting Powered Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Guest Editorial Circuit and System Design Automation for Internet of Things.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Real-Time Data Retrieval With Multiple Availability Intervals in CPS Under Freshness Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Access Characteristic Guided Read and Write Regulation on Flash Based Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Energy Optimal Task Scheduling with Normally-Off Local Memory and Sleep-Aware Shared Memory with Access Conflict.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Race to idle or not: balancing the memory sleep time with DVS for energy minimization.

[BibT_eX]

[DOI]

J. Comb. Optim., 2018

Survey of Low-Power Electric Vehicles: A Design Automation Perspective.

[BibT_eX]

[DOI]

Naehyuck Chang

IEEE Des. Test, 2018

EasyConvPooling: Random Pooling with Easy Convolution for Accelerating Training and Testing.

[BibT_eX]

[DOI]

CoRR, 2018

Work-in-Progress: Joint Network and Computing Resource Scheduling for Wireless Networked Control Systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

F2FS Aware Mapping Cache Design on Solid State Drives.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

NVLH: Crash-Consistent Linear Hashing for Non-Volatile Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

Shadow Block: Accelerating ORAM Accesses with Data Duplication.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Selective Compression Scheme for Read Performance Improvement on Flash Devices.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Near Data Filtering for Distributed Database Systems.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

An Efficient Cache Management Scheme for Capacitor Equipped Solid State Drives.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

Maximizing I/O throughput and minimizing performance variation via reinforcement learning based I/O merging for SSDs: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2018

Energy, latency, and lifetime improvements in MLC NVM with enhanced WOM code.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Emerging and Nonvolatile Memory.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Hardware/Software Codesign., 2017

CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Maximizing Common Idle Time on Multicore Processors With Shared Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Guest Editorial: Special Issue on Embedded Computing for IoT.

[BibT_eX]

[DOI]

Marilyn Wolf

Jason Xue

ACM Trans. Embed. Comput. Syst., 2017

Lightweight Data Compression for Mobile Flash Storage.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

Guest Editorial: Special Issue on LCTES 2015.

[BibT_eX]

[DOI]

Sebastian Fischmeister

Jason Xue

ACM Trans. Embed. Comput. Syst., 2017

State Asymmetry Driven State Remapping in Phase Change Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Memory-Aware Embedded Control Systems Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Special issue on: "Heterogeneous architectures for Cyber-physical systems (HACPS)".

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Data re-allocation enabled cache locking for embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2017

Improving File System Performance of Mobile Storage Systems Using a Decoupled Defragmenter.

[BibT_eX]

[DOI]

Proceedings of the 2017 USENIX Annual Technical Conference, 2017

Energy-aware morphable cache management for self-powered non-volatile processors.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

An empirical study of F2FS on mobile devices.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

Runtime and reconfiguration dual-aware placement for SRAM-NVM hybrid FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Improving read performance via selective Vpass reduction on high density 3D NAND flash memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Enhancing SSD performance with LDPC-aware garbage collection.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

Design Exploration for Multiple Level Cell Based Non-Volatile FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

On efficient message passing in energy harvesting based distributed system.

[BibT_eX]

[DOI]

Ye Tian

Qiang Xu

Jason Xue

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Improving LDPC performance via asymmetric sensing level placement on flash memory.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Write reconstruction for write throughput improvement on MLC PCM based main memory.

[BibT_eX]

[DOI]

J. Syst. Archit., 2016

Redesigning software and systems for non-volatile processors on self-powered devices.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

Energy-Aware Real-Time Task Scheduling on Local/Shared Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Real-Time Systems Symposium, 2016

Dynamic merging/splitting for better responsiveness in mobile devices.

[BibT_eX]

[DOI]

Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories.

[BibT_eX]

[DOI]

Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNs.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Refresh-aware loop scheduling for high performance low power volatile STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

An Empirical Study of File-System Fragmentation in Mobile Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the 8th USENIX Workshop on Hot Topics in Storage and File Systems, 2016

Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016

I/O scheduling with mapping cache awareness for flash based storage systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Embedded Software, 2016

Exploiting process variation for retention induced refresh minimization on flash memory.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Accurate personal ultraviolet dose estimation with multiple wearable sensors.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016

Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning.

[BibT_eX]

[DOI]

Alex Orailoglu

IEEE Trans. Very Large Scale Integr. Syst., 2015

Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Joint WCET and Update Activity Minimization for Cyber-Physical Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2015

Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Modular Performance Analysis of Energy-Harvesting Real-Time Networked Systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015

C3: Cooperative Code Positioning and Cache Locking for WCET Minimization.

[BibT_eX]

[DOI]

Fuyang Li

Proceedings of the 21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2015

Improving MLC PCM write throughput by write reconstruction.

[BibT_eX]

[DOI]

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Software assisted non-volatile register reduction for energy harvesting based cyber-physical system.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Maximizing IO performance via conflict reduction for flash memory storage systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Maximizing common idle time on multi-core processors with shared memory.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Race to idle or not: balancing the memory sleep time with DVS for energy minimization.

[BibT_eX]

[DOI]

Chenchen Fu

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Compiler directed automatic stack trimming for efficient non-volatile processors.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification.

[BibT_eX]

[DOI]

Xiang Chen

Yiran Chen

Proceedings of the 52nd Annual Design Automation Conference, 2015

Self-powered wearable sensor node: Challenges and opportunities.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

Minimizing MLC PCM write energy for free through profiling-based state remapping.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A Unified Write Buffer Cache Management Scheme for Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Error Model Guided Joint Performance and Endurance Optimization for Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Dual partitioning multicasting for high-performance on-chip networks.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Non-volatile registers aware instruction selection for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives.

[BibT_eX]

[DOI]

Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014

Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A wear-leveling-aware dynamic stack for PCM memory in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SLC-enabled Wear Leveling for MLC PCM Considering Process Variation.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Retention Trimming for Wear Reduction of Flash Memory Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM.

[BibT_eX]

[DOI]

Keni Qiu

Qing'an Li

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Algorithms to Minimize Data Transfer for Code Update on Wireless Sensor Network.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2013

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Joint variable partitioning and bank selection instruction optimization for partitioned memory architectures.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Write activity reduction on non-volatile main memories for embedded chip multiprocessors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.

[BibT_eX]

[DOI]

SIGBED Rev., 2013

Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

Data re-allocation enabled cache locking for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Compiler directed write-mode selection for high performance low power volatile PCM.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

Profit maximization through process variation aware high level synthesis with speed binning.

[BibT_eX]

[DOI]

Alex Orailoglu

Proceedings of the Design, Automation and Test in Europe, 2013

Cache coherence enabled adaptive refresh for volatile STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Software enabled wear-leveling for hybrid PCM main memory on embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Multirate controller design for resource- and schedule-constrained automotive ECUs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Minimizing code size via page selection optimization on partitioned memory architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2013

WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systems.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Instruction Cache Locking for Embedded Systems using Probability Profile.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Minimizing Access Cost for Multiple Types of Memory Units in Embedded Systems Through Data Allocation and Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2012

Hybrid nonvolatile disk cache for energy-efficient and high-performance systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Single and multiple device DSA problems, complexities and online algorithms.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2012

Instruction cache locking for multi-task real-time embedded systems.

[BibT_eX]

[DOI]

Real Time Syst., 2012

Loop fusion and reordering for register file optimization on stream processors.

[BibT_eX]

[DOI]

J. Syst. Softw., 2012

[BibT_eX]

[DOI]

J. Syst. Archit., 2012

Memory access schedule minimization for embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2012

Analysis and approximation for bank selection instruction minimization on partitioned memory architecture.

[BibT_eX]

[DOI]

J. Comb. Optim., 2012

General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size.

[BibT_eX]

Int. J. Comput. Their Appl., 2012

Guest Editorial Special Section on Memory Architectures and Organization.

[BibT_eX]

[DOI]

Nikil D. Dutt

IEEE Embed. Syst. Lett., 2012

Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012

WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012

Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Poster Abstract: Smart Phone Lift for Improving Energy Efficiency and User Comfort in Green Buildings.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems, 2012

Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mobile devices user - The subscriber and also the publisher of real-time OLED display power management plan.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TEACA: Thread ProgrEss Aware Coherence Adaption for hybrid coherence protocols.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

PRR: A low-overhead cache replacement algorithm for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory.

[BibT_eX]

[DOI]

Proceedings of the 16th Workshop on Interaction between Compilers and Computer Architectures, 2012

2011

Energy-Efficient Joint Scheduling and Application-Specific Interconnection Design.

[BibT_eX]

[DOI]

Cathy Qun Xu

IEEE Trans. Very Large Scale Integr. Syst., 2011

Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2011

Sleep-aware mode assignment in wireless embedded systems.

[BibT_eX]

[DOI]

Zhaohui Yuan

Yuping Zhang

J. Parallel Distributed Comput., 2011

Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2011

Acceleration of Composite Order Bilinear Pairing on Graphics Hardware.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2011

STT-RAM based energy-efficiency hybrid cache for CMPs.

[BibT_eX]

[DOI]

Jianhua Li

Yinlong Xu

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded Systems.

[BibT_eX]

[DOI]

Qing'an Li

Proceedings of the IEEE 10th International Conference on Trust, 2011

Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems.

[BibT_eX]

[DOI]

Liang Shi

Xuehai Zhou

Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

Optimal task allocation on non-volatile memory based hybrid main memory.

[BibT_eX]

[DOI]

Proceedings of the Research in Applied Computation Symposium, 2011

Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

ExLRU: a unified write buffer cache management for flash memory.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Embedded Software, 2011

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Emerging non-volatile memories: opportunities and challenges.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Optimizing Memory Cost with Loop Transformations.

[BibT_eX]

Meilin Liu

Andrew McClain

Chun Xue

Proceedings of the ISCA 26th International Conference on Computers and Their Applications, 2011

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Variable Length Pattern Matching for Hardware Network Intrusion Detection System.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2010

Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2010

Fine-grained adaptive CMP cache sharing through access history exploitation.

[BibT_eX]

[DOI]

Chengmo Yang

Alex Orailoglu

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Optimal scheduling to minimize non-volatile memory access time with hardware cache.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Minimizing write activities to non-volatile memory via scheduling and recomputation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Single and Multiple Device DSA Problem, Complexities and Online Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Computation - 21st International Symposium, 2010

Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC.

[BibT_eX]

[DOI]

Proceedings of the 39th International Conference on Parallel Processing, 2010

LADPM: Latency-Aware Dual-Partition Multicast Routing for Mesh-Based Network-on-Chips.

[BibT_eX]

[DOI]

Jianhua Li

Yinlong Xu

Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

Write activity reduction on flash main memory via smart victim cache.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Energy efficient joint scheduling and multi-core interconnect design.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Optimizing scheduling and intercluster connection for application-specific DSP processors.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2009

Loop scheduling and bank type assignment for heterogeneous multi-bank memory.

[BibT_eX]

[DOI]

Laurence Tianruo Yang

J. Parallel Distributed Comput., 2009

Optimizing parallelism for nested loops with iterational and instructional retiming.

[BibT_eX]

[DOI]

J. Embed. Comput., 2009

Energy minimization for heterogeneous wireless sensor networks.

[BibT_eX]

[DOI]

J. Embed. Comput., 2009

Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Real-Time and Embedded Technology and Applications Symposium, 2009

Reprogramming with Minimal Transferred Data on Wireless Sensor Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th International Conference on Mobile Adhoc and Sensor Systems, 2009

Minimizing Memory Access Schedule for Memories.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2009 Workshops), 2009

Loop Fusion Technique with Minimal Memory Cost via Retiming.

[BibT_eX]

Proceedings of the ISCA 24th International Conference on Computers and Their Applications, 2009

Energy-aware register file re-partitioning for clustered VLIW architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Computation and data transfer co-scheduling for interconnection bus minimization.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Timing optimization via nest-loop pipelining considering code size.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

Minimizing Transferred Data for Code Update on Wireless Sensor Network.

[BibT_eX]

[DOI]

Proceedings of the Wireless Algorithms, 2008

Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008

Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.

[BibT_eX]

[DOI]

Proceedings of the Distributed Embedded Systems: Design, 2008

A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Distributed Computing Systems (ICDCS 2008), 2008

Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2008

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

QoS for Networked Heterogeneous Real-Time Embedded Systems.

[BibT_eX]

Proceedings of the ISCA 21st International Conference on Parallel and Distributed Computing and Communication Systems, 2008

2007

Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping.

[BibT_eX]

[DOI]

Chun Xue

Zili Shao

J. VLSI Signal Process., 2007

Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Parallel Network Intrusion Detection on Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Loop scheduling with timing and switching-activity minimization for VLIW DSP.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Design optimization and space minimization considering timing and code size via retiming and unfolding.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2006

Algorithms and analysis of scheduling for loops with minimum switching.

[BibT_eX]

[DOI]

Int. J. Comput. Sci. Eng., 2006

Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Loop Striping: Maximize Parallelism for Nested Loops.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Optimizing Timing and Code Size Using Maximum Direct Loop Fusion.

[BibT_eX]

Meilin Liu

Chun Xue