Michael Ashburn

According to our database, Michael Ashburn authored at least 5 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD.

Ayman Shabra, Padraig Cooney, Adalberto Cantoni, Joshua Bamford, Stacy Ho, Michael Ashburn

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR.

Tao He, Michael Ashburn, Stacy Ho, Yi Zhang, Gabor C. Temes

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS.

Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Frank Opteynde, Michael Ashburn

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2013

An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency.

Patrick Riehl, Paul Fowers, Hao-Ping Hong, Michael Ashburn

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation.

Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013