Michael C. W. Coln

According to our database1, Michael C. W. Coln authored at least 14 papers between 1985 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
A 1-V 560-nW SAR ADC With 90-dB SNDR for IoT Sensing Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018
A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS.
IEEE J. Solid State Circuits, 2018

Corrections to "Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results".
IEEE J. Solid State Circuits, 2018

Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results.
IEEE J. Solid State Circuits, 2018

A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016
A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2013
A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability.
IEEE J. Solid State Circuits, 2013

A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013

2011
All-Digital Background Calibration of a Successive Approximation ADC Using the "Split ADC" Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2009
"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Digital Background-Calibration Algorithm for "Split ADC" Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2006
Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC".
IEEE J. Solid State Circuits, 2006

1985
A high performance dielectric measurement system.
PhD thesis, 1985


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