Michael H. Perrott

According to our database, Michael H. Perrott authored at least 33 papers between 1997 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A 0.5 V < 4 µW CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor.

Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott

IEEE J. Solid State Circuits, 2014

A clockless, multi-stable, CMOS analog circuit.

Mohammad Alhawari, Michael H. Perrott

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter.

Michael H. Perrott, James C. Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi

IEEE J. Solid State Circuits, 2013

Session 15 overview: Data converter techniques.

Michael H. Perrott, Geert Van der Plas

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer.

Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability.

Michael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation.

Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

A Time-Domain Resolution Improvement of an RF-DAC.

Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator.

Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp

IEEE J. Solid State Circuits, 2010

A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator.

Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping.

Matthew Z. Straayer, Michael H. Perrott

IEEE J. Solid State Circuits, 2009

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 µm CMOS.

Matthew Park, Michael H. Perrott

IEEE J. Solid State Circuits, 2009

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop.

Belal Helal, Chun-Ming Hsu, Kerwin Johnson, Michael H. Perrott

IEEE J. Solid State Circuits, 2009

A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer.

Min C. Park, Michael H. Perrott

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A VCO-based Analog-to-digital Converter with Second-order Sigma-Delta Noise Shaping.

Min C. Park, Michael H. Perrott

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Single-slope 80MS/s ADC using Two-Step Time-to-Digital Conversion.

Min C. Park, Michael H. Perrott

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer.

Matthew Z. Straayer, Michael H. Perrott

IEEE J. Solid State Circuits, 2008

A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation.

Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott

IEEE J. Solid State Circuits, 2008

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance.

Belal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott

IEEE J. Solid State Circuits, 2008

A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation.

Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition.

Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore

IEEE J. Solid State Circuits, 2006

A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise.

Scott E. Meninger, Michael H. Perrott

IEEE J. Solid State Circuits, 2006

A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation.

Ethan Crain, Michael H. Perrott

IEEE J. Solid State Circuits, 2006

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter.

Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

A numerical design approach for high speed, differential, resistor-loaded, CMOS amplifiers.

Ethan Crain, Michael H. Perrott

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Guest editorial.

Michael H. Perrott, Gu-Yeon Wei

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise.

Scott E. Meninger, Michael H. Perrott

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm.

Charlotte Y. Lau, Michael H. Perrott

Proceedings of the 40th Design Automation Conference, 2003

2002

A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis.

Michael H. Perrott, Mitchell D. Trott, Charles G. Sodini

IEEE J. Solid State Circuits, 2002

Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits.

Michael H. Perrott

IEEE Des. Test Comput., 2002

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.

Michael H. Perrott

Proceedings of the 39th Design Automation Conference, 2002

1997

Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers.

Michael H. Perrott

PhD thesis, 1997

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation.

Michael H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini

IEEE J. Solid State Circuits, 1997