Geert Van der Plas

According to our database1, Geert Van der Plas authored at least 96 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor.
IEEE Trans. Very Large Scale Integr. Syst., 2022


(Why do we need) Wireless Heterogeneous Integration (anyway?).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Design and Technology Solutions for 3D Integrated High Performance Systems.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited).
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

2019
Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Process Complexity and Cost Considerations of Multi-Layer Die Stacks.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
A study on substrate noise coupling among TSVs in 3D chip stack.
IEICE Electron. Express, 2018

TSV process-induced MOS reliability degradation.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Thermal experimental and modeling analysis of high power 3D packages.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Through silicon via to FinFET noise coupling in 3-D integrated circuits.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Processing active devices on Si interposer and impact on cost.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling.
Microelectron. Reliab., 2014

Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Analysis of 3D interconnect performance: Effect of the Si substrate resistivity.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Session 15 overview: Data converter techniques.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Design issues in heterogeneous 3D/2.5D integration.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter.
IEEE J. Solid State Circuits, 2012

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
Low-Power ADCs for Bio-Medical Applications.
Proceedings of the Bio-Medical CMOS ICs, 2011

Fine grain thermal modeling and experimental validation of 3D-ICs.
Microelectron. J., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.
Proceedings of the Design, Automation and Test in Europe, 2011

3D heterogeneous system integration: application driver for 3D technology development.
Proceedings of the 48th Design Automation Conference, 2011

DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Analysis of microbump induced stress effects in 3D stacked IC technologies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

In-tier diagnosis of power domains in 3D TSV ICs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors.
IEEE Trans. Instrum. Meas., 2010

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010

A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS.
IEEE J. Solid State Circuits, 2010

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


3D integration: Circuit design, test, and reliability challenges.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5-7 GHz LC -VCO.
IEEE Trans. Instrum. Meas., 2009

A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2009

A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS.
IEEE J. Solid State Circuits, 2009

A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs.
IEICE Trans. Electron., 2009

Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters.
IEICE Trans. Electron., 2009

A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
The Potential of FinFETs for Analog and RF Circuit Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.
IEEE J. Solid State Circuits, 2007

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a.
IEEE J. Solid State Circuits, 2007

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Scalable Gate-Level Models for Power and Timing Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
SWAN: high-level simulation methodology for digital substrate noise generation.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Evolution of substrate noise generation mechanisms with CMOS technology scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate.
IEEE J. Solid State Circuits, 2006

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling.
EURASIP J. Wirel. Commun. Netw., 2006

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Digital ground bounce reduction by supply current shaping and clock frequency Modulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates.
IEEE J. Solid State Circuits, 2005

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.
Proceedings of the 2005 Design, 2005

Substrate noise immune design of an LC-tank VCO using sensitivity functions.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
IEEE J. Solid State Circuits, 2004

Digital Ground Bounce Reduction by Phase Modulation of the Clock.
Proceedings of the 2004 Design, 2004

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
Proceedings of the 41th Design Automation Conference, 2004

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
CYCLONE: automated design and layout of RF LC-oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A layout synthesis methodology for array-type analog blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
AMGIE-A synthesis environment for CMOS analog integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Layout-Aware Synthesis Methodology for RF Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
CYCLONE: automated design and layout of RF LC-oscillators.
Proceedings of the 37th Conference on Design Automation, 2000

Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter.
Proceedings of the 37th Conference on Design Automation, 2000

1999
A 14-bit intrinsic accuracy Q<sup>2</sup> random walk CMOS DAC.
IEEE J. Solid State Circuits, 1999

Statistical behavioral modeling for A/D-converters.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1997
Automated test pattern generation for analog integrated circuits.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1996

1995
An analogue module generator for mixed analogue/digital asic design.
Int. J. Circuit Theory Appl., 1995


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