Belal Helal

According to our database1, Belal Helal authored at least 8 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019

2017
A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

2010
A 1.2 mm<sup>2</sup> fully integrated GPS radio with cellular/WiFi Co-existence.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop.
IEEE J. Solid State Circuits, 2009

2008
Techniques for low jitter clock multiplication.
PhD thesis, 2008

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance.
IEEE J. Solid State Circuits, 2008


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