Michael Payer

According to our database1, Michael Payer authored at least 17 papers between 1980 and 2003.

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Bibliography

2003
A Platform for Construction and Integration of Digital IP Blocks.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

2001
Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation).
Informationstechnik Tech. Inform., 2001

2000
Industrial Experience with Formal Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

1995
Model Checking in Industrial Hardware Design.
Proceedings of the 32st Conference on Design Automation, 1995

1993
The Siemens high-level synthesis system CALLAS.
IEEE Trans. Very Large Scale Integr. Syst., 1993

1992
Allocation algorithms based on path analysis.
Integr., 1992

Data Part Optimizations in the CALLAS Synthesis Environment.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

1991
Partitioning and ordering of CMOS circuits for switch level analysis.
Integr., 1991

Scheduling under resource constraints and module assignment.
Integr., 1991

Area and performance optimizations in path-based scheduling.
Proceedings of the conference on European design automation, 1991

Data-Path Synthesis Using Path Analysis.
Proceedings of the 28th Design Automation Conference, 1991

1989
Graphentheoretische Ansätze für CAD-Werkzeuge in der CMOS-Technik.
PhD thesis, 1989

Finite State Machine Theory as a Tool for Construction of Systolic Arrays.
Proceedings of the Computer Aided Systems Theory - EUROCAST'89, A Selection of Papers from the International Workshop EUROCAST'89, Las Palmas, Spain, February 26, 1989

1988
A system for estimation of numerical stability for matrix operations in systolic arrays.
Microprocess. Microprogramming, 1988

Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-Schaltungen.
Proceedings of the GI, 1988

1987
Verification and validation of hierarchical CMOS gate array layouts.
Microprocess. Microprogramming, 1987

1980
Systematischer Entwurf von Makroprozessoren.
Proceedings of the GI - 10. Jahrestagung, Saarbrücken, 30. September, 1980


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