Reinaldo A. Bergamaschi

Affiliations:
  • University of Campinas, Sao Paulo, Brazil


According to our database1, Reinaldo A. Bergamaschi authored at least 63 papers between 1988 and 2014.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to the development of system design tools and methodologies.".

Timeline

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Bibliography

2014
Adaptive global power optimization for Web servers.
J. Supercomput., 2014

The Odysci Academic Search System.
D Lib Mag., 2014

Empirical and analytical approaches for web server power modeling.
Clust. Comput., 2014

2013
Introductions to special issue on ESWEEK 2011.
Des. Autom. Embed. Syst., 2013

2012
Data center power and performance optimization through global selection of P-states and utilization rates.
Sustain. Comput. Informatics Syst., 2012

A quantitative analysis of WWW, hypertext and JCDL conferences in the last decade.
SIGWEB Newsl., 2012

2011
Announcement: introducing Odysci.
ACM SIGACCESS Access. Comput., 2011

Empirical Web server power modeling and characterization.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

2010
ESWEEK 2009 special issue introduction.
Des. Autom. Embed. Syst., 2010

2009
ESWEEK 2007 special issue introduction.
Des. Autom. Embed. Syst., 2009

2008
The State of ESL Design [Roundtable].
IEEE Des. Test Comput., 2008

Challenges of the nanoscale era.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Exploring power management in multi-core systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Heterogeneous Behavioral Hierarchy Extensions for SystemC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Embedded Systems Week.
IEEE Des. Test Comput., 2007

Performance modeling for early analysis of multi-core systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Heterogeneous behavioral hierarchy for system level designs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Blue Gene/L compute chip: Memory and Ethernet subsystem.
IBM J. Res. Dev., 2005

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.
Des. Autom. Embed. Syst., 2005

Second special issue on SystemC.
Des. Autom. Embed. Syst., 2005

Editors' introduction.
Des. Autom. Embed. Syst., 2005


2004
Early and accurate analysis of SoCs: oxymoron or real?
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

System level design: six success stories in search of an industry.
Proceedings of the 41th Design Automation Conference, 2004

2003
Simplifying SoC design with the Customizable Control Processor Platform.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Modeling and Integration of Peripheral Devices in Embedded Systems.
Proceedings of the 2003 Design, 2003

State-based power analysis for systems-on-chip.
Proceedings of the 40th Design Automation Conference, 2003

SEAS: a system for early analysis of SoCs.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

The future of system-level design: can we find the right solutions to the right problems at the right time?
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

System-level design tools: who needs them, who has them, and how much should they cost?
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Modeling and Integration of Peripheral Devices in Embedded Systems.
Proceedings of the Embedded Software for SoC, 2003

2002
Bridging the domains of high-level and logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Early analysis tools for system-on-a-chip design.
IBM J. Res. Dev., 2002

The A to Z of SoCs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Automating the Design of SOCs Using Cores.
IEEE Des. Test Comput., 2001

2000
Designing systems-on-chip using cores.
Proceedings of the 37th Conference on Design Automation, 2000

Coral-automating the design of systems-on-chip using cores.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Panel Statement: System-Level Design: Designers' Wish List vs. Reality.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Synthesis of Arrays and Records.
Proceedings of the IEEE International Conference On Computer Design, 1999

Embedded Java: techniques and applications (tutorial abstract).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Don't cares in synthesis: theoretical pitfalls and practical solutions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Observable Time Windows: Verifying High-Level Synthesis Results.
IEEE Des. Test Comput., 1997

Generalized resource sharing.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Observable Time Windows: Verifying the Results of High-Level Synthesis.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
High-level synthesis in an industrial environment.
IBM J. Res. Dev., 1995

Be careful with don't cares.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Efficient use of large don't cares in high-level and logic synthesis.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?
Proceedings of the 32st Conference on Design Automation, 1995

1993
A system for production use of high-level synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 1993

1992
Allocation algorithms based on path analysis.
Integr., 1992

High-Level State Machine Specification and Synthesis.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Timing analysis in high-level synthesis.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Control Optimization in High-Level Synthesis Using Behavioral Don't Cares.
Proceedings of the 29th Design Automation Conference, 1992

1991
SKOL: a system for logic synthesis and technology mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Scheduling under resource constraints and module assignment.
Integr., 1991

The Effects of False Paths in High-Level Synthesis.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Area and performance optimizations in path-based scheduling.
Proceedings of the conference on European design automation, 1991

Data-Path Synthesis Using Path Analysis.
Proceedings of the 28th Design Automation Conference, 1991

1990
Redesign using state splitting.
Proceedings of the European Design Automation Conference, 1990

Synthesis Using Path-Based scheduling: algorithms and Exercises.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988
Automatic synthesis and technology mapping of combinational logic.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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