Mike Mantor

According to our database1, Mike Mantor authored at least 16 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution.
ACM Trans. Archit. Code Optim., 2019

7NM "NAVI" GPU - A GPU Built for Performance and Efficiency.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

2018
GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP.
ACM Trans. Archit. Code Optim., 2018

2016
A model-driven approach to warp/thread-block level GPU cache bypassing.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Revisiting ILP Designs for Throughput-Oriented GPGPU Architecture.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

2014
Kabini: An AMD Accelerated Processing Unit System on A Chip.
IEEE Micro, 2014

A Case for a Flexible Scalar Unit in SIMT Architecture.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013
Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement.
Proceedings of the International Conference on Supercomputing, 2013

2012
A unified optimizing compiler framework for different GPGPU architectures.
ACM Trans. Archit. Code Optim., 2012

Fixing Performance Bugs: An Empirical Study of Open-Source GPGPU Programs.
Proceedings of the 41st International Conference on Parallel Processing, 2012

CPU-assisted GPGPU on fused CPU-GPU architectures.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

AMD Radeon™ HD 7970 with graphics core next (GCN) architecture.
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

Shared memory multiplexing: a novel way to improve GPGPU throughput.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2010
Accelerating MATLAB Image Processing Toolbox functions on GPUs.
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, 2010

2009
Understanding software approaches for GPGPU reliability.
Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, 2009


  Loading...