Mike Ignatowski

According to our database, Mike Ignatowski authored at least 22 papers between 2001 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

A Research Retrospective on AMD's Exascale Computing Journey.

Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, René van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2019

Power Profiling of Modern Die-Stacked Memory.

Dylan C. Stow, Amin Farmahini Farahani, Sudhanva Gurumurthi, Michael Ignatowski, Yuan Xie

IEEE Comput. Archit. Lett., 2019

Co-ML: a case for <u>co</u>llaborative <u>ML</u> acceleration using near-data processing.

Shaizeen Aga, Nuwan Jayasena, Mike Ignatowski

Proceedings of the International Symposium on Memory Systems, 2019

2018

Challenges of High-Capacity DRAM Stacks and Potential Directions.

Amin Farmahini Farahani, Sudhanva Gurumurthi, Gabriel H. Loh, Michael Ignatowski

Proceedings of the Workshop on Memory Centric High Performance Computing, 2018

2017

Exploring the Processing-in-Memory design space.

Marko Scrbak, Mahzabeen Islam, Krishna M. Kavi, Mike Ignatowski, Nuwan Jayasena

J. Syst. Archit., 2017

Design and Analysis of an APU for Exascale Computing.

Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2015

Achieving Exascale Capabilities through Heterogeneous Computing.

Michael J. Schulte, Mike Ignatowski, Gabriel H. Loh, Bradford M. Beckmann, William C. Brantley, Sudhanva Gurumurthi, Nuwan Jayasena, Indrani Paul, Steven K. Reinhardt, Gregory Rodgers

IEEE Micro, 2015

Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy.

Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski

J. Syst. Archit., 2015

Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories.

Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

NMI: A new memory interface to enable innovation.

David Roberts, Amin Farmahini Farahani, Kevin Cheng, Nathan Hu, David Mayhew, Michael Ignatowski

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Processing-in-Memory: Exploring the Design Space.

Marko Scrbak, Mahzabeen Islam, Krishna M. Kavi, Mike Ignatowski, Nuwan Jayasena

Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2014

Toward efficient programmer-managed two-level memory hierarchies in exascale computers.

Mitesh R. Meswani, Gabriel H. Loh, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski

Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, 2014

TOP-PIM: throughput-oriented programmable processing in memory.

Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Lifan Xu, Michael Ignatowski

Proceedings of the 23rd International Symposium on High-Performance Parallel and Distributed Computing, 2014

Improving Node-Level MapReduce Performance Using Processing-in-Memory Technologies.

Mahzabeen Islam, Marko Scrbak, Krishna M. Kavi, Mike Ignatowski, Nuwan Jayasena

Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

3D DRAM and PCMs in Processor Memory Hierarchy.

Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski

Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014

2013

A new perspective on processing-in-memory architecture design.

Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Mitesh R. Meswani, Mark Nutter, Mike Ignatowski

Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2013

A Multi-core Memory Organization for 3-D DRAM as Main Memory.

Jared Sherman, Krishna M. Kavi, Brandon Potter, Mike Ignatowski

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012

New Memory Organizations for 3D DRAM and PCMs.

Ademola Fawibe, Jared Sherman, Krishna M. Kavi, Mike Ignatowski, David Mayhew

Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2008

Technology, CAD tools, and designs for emerging 3D integration technology.

Syed M. Alam, Mike Ignatowski, Yuan Xie

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Interconnects in the Third Dimension: Design Challenges for 3D ICs.

Kerry Bernstein, Paul S. Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steven J. Koester, John Magerlein, Ruchir Puri, Albert M. Young

Proceedings of the 44th Design Automation Conference, 2007

2005

Exploitation of optical interconnects in future server architectures.

Alan F. Benner, Michael Ignatowski, Jeffrey A. Kash, Daniel M. Kuchta, Mark B. Ritter

IBM J. Res. Dev., 2005

2001

Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory.

Richard E. Matick, Thomas J. Heller, Michael Ignatowski

IBM J. Res. Dev., 2001