Mikhail Asiatici

According to our database, Mikhail Asiatici authored at least 14 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs.

Mikhail Asiatici, Paolo Ienne

ACM Trans. Reconfigurable Technol. Syst., 2022

2021

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities.

Mikhail Asiatici

PhD thesis, 2021

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System.

Mikhail Asiatici, Damian Maiorano, Paolo Ienne

J. Signal Process. Syst., 2021

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses.

Mikhail Asiatici, Paolo Ienne

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort.

Mikhail Asiatici, Damian Maiorano, Paolo Ienne

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips.

Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne

IEEE Access, 2019

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA.

Gabor Csordas, Mikhail Asiatici, Paolo Ienne

Proceedings of the International Conference on Field-Programmable Technology, 2019

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses.

Mikhail Asiatici, Paolo Ienne

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs.

Mikhail Asiatici, Paolo Ienne

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires.

Miku J. Laakso, Simon J. Bleiker, Jessica Liljeholm, Gustaf E. Martensson, Mikhail Asiatici, Andreas C. Fischer, Göran Stemme, Thorbjorn Ebefors, Frank Niklaus

IEEE Access, 2018

LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only).

Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS⁵)(Abstract Only).

Mikhail Asiatici, Damian Maiorano, Paolo Ienne

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

Virtualized Execution Runtime for FPGA Accelerators in the Cloud.

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne

IEEE Access, 2017

2016

Designing a virtual runtime for FPGA accelerators in the cloud.

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016