Nithin George

According to our database1, Nithin George
  • authored at least 10 papers between 2012 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2017
Virtualized Execution Runtime for FPGA Accelerators in the Cloud.
IEEE Access, 2017

Design Space Exploration of LDPC Decoders Using High-Level Synthesis.
IEEE Access, 2017

2016
Enriching C-based High-Level Synthesis with parallel pattern templates.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Designing a virtual runtime for FPGA accelerators in the cloud.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Automatic support for multi-module parallelism from computational patterns.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Hardware system synthesis from Domain-Specific Languages.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Making domain-specific hardware synthesis tools cost-efficient.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012


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