Mindaugas Drazdziulis

According to our database, Mindaugas Drazdziulis authored at least 7 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

Overdrive Power-Gating Techniques for Total Power Minimization.

Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.

Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

A low-leakage twin-precision multiplier using reconfigurable power gating.

Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Evaluation of power cut-off techniques in the presence of gate leakage.

Mindaugas Drazdziulis, Per Larsson-Edefors

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A gate leakage reduction strategy for future CMOS circuits.

Mindaugas Drazdziulis, Per Larsson-Edefors

Proceedings of the ESSCIRC 2003, 2003