Lars Bengtsson

Orcid: 0000-0001-6897-327X

According to our database1, Lars Bengtsson authored at least 34 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Barriers to continuance use of cloud computing: Evidence from two case studies.
Inf. Manag., July, 2023

2021
Business Model Flexibility and Software-intensive Companies: Opportunities and Challenges.
e Informatica Softw. Eng. J., 2021

2020
One size does not even fit one: supply chain strategies in the decline phase.
Int. J. Manuf. Technol. Manag., 2020

The implications of digitalization on business model change.
CoRR, 2020

2017
A High Throughput Anticollision Protocol to Decrease the Energy Consumption in a Passive RFID System.
Wirel. Commun. Mob. Comput., 2017

New design ideas for TDR-based liquid level detectors.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017

2016
An Energy and Identification Time Decreasing Procedure for Memoryless RFID Tag Anticollision Protocols.
IEEE Trans. Wirel. Commun., 2016

Computer and Smartphone Continuance Intention: A Motivational Model.
J. Comput. Inf. Syst., 2016

Appropriability: a key to opening innovation internationally?
Int. J. Technol. Manag., 2016

2013
Exploiting supplier innovativeness through knowledge integration.
Int. J. Technol. Manag., 2013

Managing a strategic source of innovation: Online users.
Int. J. Inf. Manag., 2013

2010
An Energy and Application Scenario Aware Active RFID Protocol.
EURASIP J. Wirel. Commun. Netw., 2010

UCHPC 2010: Third Workshop on UnConventional High Performance Computing.
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

2009
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems.
J. Signal Process. Syst., 2009

Manufacturing competence: a key to successful supplier integration.
Int. J. Manuf. Technol. Manag., 2009

User certification of workplace software: assessing both artefact and usage.
Behav. Inf. Technol., 2009

2008
Outsourcing manufacturing and its effect on engineering firm performance.
Int. J. Technol. Manag., 2008

Selecting back off algorithm in active RFID CSMA/CA based medium-access protocols.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

2007
Continuous improvement capability in the Swedish engineering industry.
Int. J. Technol. Manag., 2007

Protocols for Active RFID - The Energy Consumption Aspect.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Towards an Energy Efficient Protocol for Active RFID.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Reverse conversion architectures for signed-digit residue number systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Jalapeno: secentralized grid computing using peer-to-peer technology.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.
Proceedings of the Integrated Circuit and System Design, 2004

2003
A VLSI Array Architecture for Artificial Neural Networks.
Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, 2003

DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.
Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003

Arithmetic Circuits Combining Residue and Signed-Digit Representations.
Proceedings of the Advances in Computer Systems Architecture, 2003

2001
Synchronizing a High-Speed SIMD Processor Array.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

1999
Clock Speed Limitation and Timing in a Radar Signal Processing Architecture.
Proceedings of the Signal and Image Processing (SIP), 1999

1997
REMAP-γ: A Scalable SIMD VLSI Architecture with Hierarchical Control.
PhD thesis, 1997

1993
A processor array module for distributed, massively parallel, embedded computing.
Microprocess. Microprogramming, 1993


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