Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

2021

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder.

[BibT_eX]

[DOI]

Vikram Jain

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

2020

ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019

Hardware Considerations for Selection Networks.

[BibT_eX]

[DOI]

Kenneth Peter

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Energy-Efficient Soft-Assisted Product Decoders.

[BibT_eX]

[DOI]

Alireza Sheikh

Alexandre Graell i Amat

Gianluigi Liva

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication.

[BibT_eX]

[DOI]

Vikram Jain

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

Custom versus Cell-Based ASIC Design for Many-Channel Correlators.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Energy-Efficient High-Throughput Staircase Decoders.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI.

[BibT_eX]

[DOI]

Kevin Cushon

Peter A. Andrekson

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels.

[BibT_eX]

[DOI]

Lars Lundberg

Proceedings of the European Conference on Optical Communication, 2018

ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filters.

[BibT_eX]

[DOI]

Sebastian Johansson-Mauricio

Proceedings of the European Conference on Optical Communication, 2018

2017

A framework for a relative real-time tracking system based on ultra-wideband technology.

[BibT_eX]

[DOI]

Proceedings of the 14th Workshop on Positioning, Navigation and Communications, 2017

Time-domain digital back propagation: Algorithm and finite-precision implementation aspects.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Finite-Precision Optimization of Time-Domain Digital Back Propagation by Inter-Symbol Interference Minimization.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Optical Communication, 2017

Improved Low-Power LDPC FEC for Coherent Optical Systems.

[BibT_eX]

[DOI]

Kevin Cushon

Peter A. Andrekson

Proceedings of the European Conference on Optical Communication, 2017

Instruction level energy model for the Adapteva Epiphany multi-core processor.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2017

2016

Dynamic equalizer power dissipation optimization.

[BibT_eX]

[DOI]

Pontus Johannisson

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Logic filter cache for wide-VDD-range processors.

[BibT_eX]

[DOI]

Oskar Andersson

Joachim Neves Rodrigues

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Practical way halting by speculatively accessing halt tags.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Redesigning a tagless access buffer to require minimal ISA changes.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

2015

Improving Data Access Efficiency by Using Context-Aware Loads and Stores.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015

Exploring early and late ALUs for single-issue in-order pipelines.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Impact of forward error correction on energy consumption of VCSEL-based transmitters.

[BibT_eX]

[DOI]

Krzysztof Szczerba

Petter Westbergh

Alexandre Graell i Amat

Proceedings of the European Conference on Optical Communication, 2015

Energy-efficient soft-decision LDPC FEC For long-haul optical communication.

[BibT_eX]

[DOI]

Kevin Cushon

Peter A. Andrekson

Proceedings of the European Conference on Optical Communication, 2015

2014

1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis.

[BibT_eX]

[DOI]

Anders Emrich

Stefan Back Andersson

IEEE J. Solid State Circuits, 2014

Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration.

[BibT_eX]

[DOI]

Kjell O. Jeppson

Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD<sup>3</sup>).

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Designing a practical data filter cache to improve both energy efficiency and performance.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

FlexCore: Implementing an exposed datapath processor.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment.

[BibT_eX]

[DOI]

Kjell O. Jeppson

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Manufacturable nanometer designs using standard cells with regular layout.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

A SiGe 8-channel comparator for application in a synthetic aperture radiometer.

[BibT_eX]

[DOI]

Stefan Back Andersson

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Speculative tag access for reduced energy dissipation in set-associative L1 data caches.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Improving data access efficiency by using a tagless access buffer (TAB).

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012

Configurable RTL model for level-1 caches.

[BibT_eX]

[DOI]

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Data-Width-Driven Power Gating of Integer Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Viterbi Accelerator for Embedded Processor Datapaths.

[BibT_eX]

[DOI]

Kashan Khurshid Ansari

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011

Application-Specific Energy Optimization of General-Purpose Datapath Interconnect.

[BibT_eX]

[DOI]

Babak Hidaji

Salar Alipour

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Reconfigurable Instruction Decoding for a Wide-Control-Word Processor.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry.

[BibT_eX]

[DOI]

Anders Emrich

Stefan Back Andersson

J. Riesbeck

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

On-chip power supply noise and its implications on timing.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor.

[BibT_eX]

[DOI]

Muhammad Waqar Azhar

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Design space exploration for an embedded processor with flexible datapath interconnect.

[BibT_eX]

[DOI]

Ulf Jalmbrant

Erik der Hagopian

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Multiplication Acceleration Through Twin Precision.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Scheduling for an Embedded Architecture with a Flexible Datapath.

[BibT_eX]

[DOI]

Thomas Schilling

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Layout exploration of geometrically accurate arithmetic circuits.

[BibT_eX]

[DOI]

Emil Axelsson

Mary Sheeran

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree.

[BibT_eX]

[DOI]

Patrik Kimfors

Niklas Broman

Andreas Haraldsson

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

Time-domain interconnect characterisation flow for appropriate model segmentation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Noise Interaction Between Power Distribution Grids and Substrate.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

A Flexible Datapath Interconnect for Embedded Applications.

[BibT_eX]

[DOI]

Magnus Björk

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Overdrive Power-Gating Techniques for Total Power Minimization.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Multiplier reduction tree with logarithmic logic depth and regular connectivity.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A low-leakage twin-precision multiplier using reconfigurable power gating.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accounting for the skin effect during repeater insertion.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

On Maximum Current Estimation in CMOS Digital Circuits.

[BibT_eX]

[DOI]

Dainius Ciuplys

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

On Skin Effect in On-Chip Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Dynamic pass-transistor dot operators for efficient parallel-prefix adders.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Glitch-conscious low-power design of arithmetic circuits.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Evaluation of power cut-off techniques in the presence of gate leakage.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An Efficient Twin-Precision Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A power cut-off technique for gate leakage suppression [CMOS logic circuits].

[BibT_eX]

[DOI]

Mindaugas Draidiiulis

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Mixed-Mode Delay-Locked-Loop Architecture.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A gate leakage reduction strategy for future CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2003, 2003

Full-custom vs. standard-cell design flow: an adder case study.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A deep submicron power estimation methodology adaptable to variations between power characterization and estimation.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.

[BibT_eX]

Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003

2001

A regular parallel multiplier which utilizes multiple carry-propagate adders.

[BibT_eX]

[DOI]

William P. Marnane

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Cycle-true leakage current modeling for CMOS gates.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

VLSI implementation of CRC-32 for 10 Gigabit Ethernet.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Interconnect-Driven Short-Circuit Power Modeling.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000

Impact of Voltage Scaling on Glitch Power Consumption.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

An interconnect-driven design of a DFT processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

GLMC: interconnect length estimation by growth-limited multifold clustering.

[BibT_eX]

[DOI]

Christer Svensson

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A leakage-tolerant multi-phase keeper for wide domino circuits.

[BibT_eX]

[DOI]

Christer Svensson

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.

[BibT_eX]

[DOI]

Christer Svensson

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A Miniature Serial-Data SIMD Architecture.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1996

Technology mapping onto very-high-speed standard CMOS hardware.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier.

[BibT_eX]

[DOI]