Mingyang Kou

According to our database, Mingyang Kou authored at least 11 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

NaviMap: Partial Order-Guided Neural Architecture via Deep Q-Networks for Efficient CGRA Mapping.

Mingyang Kou, Jun Zeng, Xinyu Peng, Weiqing Ji, Hailong Yao

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

VAER: Via-Aware Escape Routing for Chiplet Interconnection.

Haochang Tian, Weiqing Ji, Mingyang Kou, Chengkai Wang, Fei Li, Hailong Yao

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography.

Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Nengyong Zhu, Hailong Yao

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs.

Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography.

Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Hailong Yao

CoRR, 2024

2023

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022

NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis.

Jun Zeng, Mingyang Kou, Hailong Yao

Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference.

Jun Zeng, Mingyang Kou, Hailong Yao

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

GEML: GNN-based efficient mapping method for large loop applications on CGRA.

Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits.

Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020