Jiangyuan Gu

Orcid: 0000-0003-1190-7524

Affiliations:

Tsinghua University, Beijing, China

According to our database¹, Jiangyuan Gu authored at least 20 papers between 2016 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

2.9 A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A 28nm Speculative-Decoding LLM Processor Achieving 105-to-685µs/Token Latency for Billion-Parameter Models.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System Simulation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Computing Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design.

[BibT_eX]

[DOI]

Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025

DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2023

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow.

[BibT_eX]

[DOI]

CoRR, 2023

RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

GEML: GNN-based efficient mapping method for large loop applications on CGRA.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Mixed-granularity parallel coarse-grained reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

2017

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect.

[BibT_eX]

[DOI]

Jiangyuan Gu

Shouyi Yin

Shaojun Wei

Proceedings of the 54th Annual Design Automation Conference, 2017

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Joint Modulo Scheduling and V<sub>dd</sub> Assignment for Loop Mapping on Dual- V<sub>dd</sub> CGRAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Jiangyuan Gu

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